lekernel changed the topic of #m-labs to: Mixxeo, Migen, MiSoC & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<sb0> _florent_, "set property DRIVE " + + str(c.strength) ?
<GitHub172> [migen] sbourdeauducq pushed 2 new commits to master: http://git.io/G8swMA
<GitHub172> migen/master f6dfabf Florent Kermarrec: mibuild/xilinx_vivado.py: add set property to misc constraint
<GitHub172> migen/master 506ac0f Sebastien Bourdeauducq: Merge branch 'master' of github.com:m-labs/migen
<_florent_> yes sorry, I fixed the underscore but missed the double +...
<_florent_> thanks
<sb0> _florent_, I recommend using flen(rmap.bus.dat_w)
<sb0> it's done like that for other buses except LASMI that needs more info
<sb0> ...in general, things should be done consistently in migen, and data should not be duplicated in different attributes
<_florent_> ok I can change that
<sb0> in LASMI, we already have "aw" which is difficult to obtain otherwise (as the signal is inside the bank groups)
<sb0> so dw is acceptable
<_florent_> so if I change "busword" to "dw", it's ok for you?
<sb0> no, since this is not LASMI; additionally this has absolutely nothing to do in Bank
<sb0> "bank.bus.dw" is acceptable (for consistency with LASMI), but in that case the "dw" attribute should be set on *all* bus interfaces (and it needs to be "dw" everywhere), and all code that uses flen(bus.dat_w) changed
<sb0> the current solution is to use flen(bus.dat_w) and make an exception for LASMI as there's a lot of data to store and the address signal width is difficult to optain
<_florent_> hmm ok, so for now I will use flen(bus.dat_w) for now
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<GitHub120> [misoc] sbourdeauducq pushed 1 new commit to master: http://git.io/QJpeHA
<GitHub120> misoc/master d4833cb Florent Kermarrec: cpuif: remove limitations on csr data_width
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