rellla changed the topic of #linux-sunxi to: Allwinner/sunxi /development discussion - did you try looking at our wiki? https://linux-sunxi.org - Don't ask to ask. Just ask and wait! - https://github.com/linux-sunxi/ - Logs at http://irclog.whitequark.org/linux-sunxi - *only registered users can talk*
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<tuxd3v> hello guys
<tuxd3v> I have a BananaPi m2 zero
<tuxd3v> Mainline kernel doesn't provide hdmi,hdmi-audio,bluetooth-partially, and CSI Camera support
<tuxd3v> I mean, at DTS level.
<tuxd3v> does any one knows about some good paches for m2 zero?
<tuxd3v> thanks in advance
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<tuxd3v> can't boot up bpi m2 zero with 2021.01 uboot :/
<tuxd3v> the board doesn't even search for boot.scr..
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<tuxd3v> ok, was able to find uboot, and start kernel, but it hangs on starting kernel or serial is not updated :/
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<bauen1> re the D1, are there any more details available on any security elements of the chip ? the "press releases" where a bit light on details
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<montjoie> I didnt see any crypto details, sad:(
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<bauen1> montjoie: i also haven't found anything better than the "press release", and that after experimenting with the h6 / a64 i'm not expecting anything too "good" / "interesting" tbh
<montjoie> for my interest, crypto hw, they are never good
<apritzel> are there any kind of technical docs (user manual?) for the D1 at all?
<apritzel> (I guess crypto support is the least of our concerns ...)
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<bauen1> apritzel: in the best case allwinner will recycle a lot of peripherals, but i haven't found any technical docs yet (didn't look too closely), maybe pine64 has already gotten some
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<JoaoSchim> dear people. is anyone here familiar with a A83T board using x32 LPDDR3 memory ? I'm looking for some good examples for my own board-in-progress.
<apritzel> jernej: do you feel like posting the first part of your v2 U-Boot HDMI rework patches? Up until and including "de2: switch to public uclass functions"
<apritzel> jernej: then we could ask Anatolij to merge them now, and you have those off your back
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<apritzel> JoaoSchim: what is the problem with your board's DRAM? LPDDR3 on A83T should be supported, for instance the Sinovoip BPI M3 seems to use that
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<JoaoSchim> apritzel: Yes indeed, i have used the defconfig for BPI M3 as a template. Just not sure what memory it uses. I thought it was x16 width. Currently i just get DRAM: from u-boot SPL. looking for ways to determine whether its configuration/code or hardware issue.
<apritzel> JoaoSchim: ah, it looks like the driver only supports 8 and 16 bit bus width
<JoaoSchim> Aha, that would explain, so i need to do some coding..
<apritzel> it might just not be tested, so you can try to naively enhance to code to consider 32 bit width as well
<JoaoSchim> thank you apritzel. I will look into it. Other than https://linux-sunxi.org/DDR3 is there any good refs on lpddr3 for Allwinner you know off ?
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<apritzel> JoaoSchim: no, sorry, for DRAM docs there is basically nothing official. Sometimes there are docs from related IP used on other families
<apritzel> JoaoSchim: I'd start with setting 32-bit bus width initially (instead of 16 right now), then drop down if that fails
<apritzel> JoaoSchim: and you just need to guess the MCTL_CR_BUSW32 value
<JoaoSchim> apritzel: you're the best. thanks.
<apritzel> JoaoSchim: others have more knowledge about the A83T controller, just stay in here (or poll the log)
<JoaoSchim> will do
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<apritzel> JoaoSchim: do you have a BSP boot0 booting correctly? they sometimes tell the parameters (ZQ value)
<apritzel> JoaoSchim: also we could dump DRAM registers afterwards, to see what boot0 set up differently
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<MoeIcenowy> apritzel: BPi M3 should be 32-bit LPDDR3
<MoeIcenowy> a single LPDDR3 chip is 32-bit
<MoeIcenowy> JoaoSchim: ^
<apritzel> MoeIcenowy: I only ever see 16 or 8 bit bus width programmed in dram_sun8i_a83t.c
<MoeIcenowy> and I get the BPi M3 schematics at hand
<MoeIcenowy> it says LPDDR3_32X1
<MoeIcenowy> (and the chip has SDQ0..SDQ31
<MoeIcenowy> apritzel: it should be an error when copying constant definition from dram_sun8i_a33.c
<MoeIcenowy> A33 has 16-bit DRAM interface, but A83T has 32-bit
<MoeIcenowy> and that bit, as I know, is a "half-width" bit
<apritzel> MoeIcenowy: so it's 32 and 16 bit, really?
<MoeIcenowy> so it represents 8/16 on A33, but 16/32 on A83T
<MoeIcenowy> yes
<apritzel> makes sense, there is indeed only one chip on that board
<JoaoSchim> very much so. good insight. means my issue is hw related..
<MoeIcenowy> JoaoSchim: what happened
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<apritzel> MoeIcenowy: seems like the DRAM code hangs, no output after "DRAM: "
<apritzel> MoeIcenowy: nice, thanks
<JoaoSchim> thanks indeed. nice.
<MoeIcenowy> it disables DX2GCR0 and DX3GCR0, these registers only exist if there's 3 groups of DX
<MoeIcenowy> s/3/4
<MoeIcenowy> and one group is 8 bits
<apritzel> that's similar to the A64 code, isn't it?
<MoeIcenowy> yes
<MoeIcenowy> you got it
<MoeIcenowy> you can get that bus-width-related code is just copied from A33
<MoeIcenowy> and is wrong
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<MoeIcenowy> JoaoSchim: BTW BPi M3 schematics is publicly available
<MoeIcenowy> you can try to
<MoeIcenowy> compare it with yours
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<JoaoSchim> yeah thanks i found it. no component numbers though.. but indead 1x32 layout for sdram.
<JoaoSchim> thats a match..
<apritzel> JoaoSchim: the wiki has a hi-res picture of the board, with a bit of squinting you can make out the part number
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<JoaoSchim> found a small difference between the SDRAM BPI M3 and mine. My SDRAM has 2 dies. while BPI has single die. don't known what that entails though..
<JoaoSchim> *scratching head..
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<apritzel> JoaoSchim: so is this a dual-rank DRAM in a single package, then?
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<JoaoSchim> looks like it. I have a micron mt52l512m32d2pf-107 on board.
<JoaoSchim> d2 seems to indicate as much
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<tuxd3v> hello guys, I have a doubt.. I have in the DT this:
<tuxd3v> gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
<tuxd3v> souldn't it be:
<tuxd3v> gpios = <&r_pio 10 10 GPIO_ACTIVE_HIGH>; /* PL10 */
<tuxd3v> L=10
<tuxd3v> A=0
<tuxd3v> I mean: gpios = <&r_pio 11 10 GPIO_ACTIVE_HIGH>; /* PL10 */
<tuxd3v> L=11
<apritzel> tuxd3v: no: the "r_pio" is for PortL onwards only, so counting is relative to that
<apritzel> PM10 would be <&r_pio 1 10 ...>
<tuxd3v> what would be PA10 then?
<apritzel> <&pio 0 10 ...> (not r_pio)
<tuxd3v> ho..so pio gows from 0-10
<tuxd3v> and r_pio follows that restarting the counting?
<tuxd3v> apritzel, many thanks
<apritzel> yes
<apritzel> r_pio is meant primarily for the management controller, I think it's on a different power domain
<tuxd3v> ok, many thanks, that exlains a lot :)
<MoeIcenowy> Allwinner D1 is sun20iw1p1
<MoeIcenowy> mripard: finally Allwinner BSP starts to use sunxi-ng clk
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<jernej> apritzel: yeah, I will, but not before Monday
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<mripard> MoeIcenowy: cool :)
<mripard> do you have a link ?
<apritzel> jernej: ok, thanks!
<MoeIcenowy> mripard: not able to redistribute now
<mripard> ok :)
<wens> MoeIcenowy: hurray
<jernej> that's nice
<jernej> but is it the only driver that's reused? :)
<mripard> they've used the pinctrl driver for a while iirc
<MoeIcenowy> and they still use their cursed pack format for booting
<MoeIcenowy> they should migrate to FIT ;-)
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<jernej> is opensbi open source?
<MoeIcenowy> yes
<MoeIcenowy> it's based on C910 support which is open
<MoeIcenowy> but the C910 support upstream is really too simple
<jernej> well, the only remaining question - what about DRAM driver? :)
<MoeIcenowy> for the BSP that I received
<MoeIcenowy> it's a compiled .S
<MoeIcenowy> Jesus it's quite unreadable
<MoeIcenowy> I even want to feed the compiled .o from the .S to ghidra again
<jernej> time to learn some RISC-V asm, then :)
<MoeIcenowy> jernej: I need a good assembly reader
<MoeIcenowy> you know GCC never generates assembly for being read by *human*
<MoeIcenowy> but I am not an assembler
<anarsoul> you mean att vs intel syntax? :)
<palmer> if you guys have questions about the RISC-V stuff I'm happy to help
<palmer> I don't actually have a board yet, but I'm hoping to get one at some point
<jernej> MoeIcenowy: I'll take the challenge :)
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<swiftgeek> I guess "allwinner D1" docs are still not available?
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