<parco>
I did notice that patch was dropped from further updates, but assuming it's still correct, I'm not sure what could be causing my issues. Any help would be greatly appreciated.
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<jernej>
check comment #5 for alternative solution
<jernej>
MoeIcenowy: It looks like TCON1 works with PLL_VIDEO1, but HDMI only works with PLL_VIDEO0
<jernej>
and HDMI PHY
<jernej>
BSP uses only PLL_VIDEO0 for HDMI and TCON1
<jernej>
even HDMI blob in BSP differs between R40 and A64
<jernej>
R40 blob puts HDMI PHY on PLL_VIDEO1, while A64 blob on PLL_VIDEO0
<jernej>
so I don't think it's possible to use PLL_VIDEO1 for HDMI on A64
<jernej>
I hope TL Lim can ask someone at Allwinner
<wens>
jernej: thanks. that code movement breaking things didn't make sense to me
<jernej>
wens: I dumped that secure section and disassembled it
<jernej>
it seems there are some DRAM (>0x40000000) addresses
<jernej>
I guess they shouldn't be?
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<wens>
jernej: h3 doesn't have secure sram, so the secure section is put at the end of the DRAM, and the memory region in the dt is reduced in size accordingly
<jernej>
ah, that explains
<wens>
the data abort was probably from the interrupt vector not being aligned
<wens>
just before u-boot "boots", it sets up the secure monitor stuff, and jumps to it through an smc call, and when it returns it is then non-secure, and ready to jump to the kernel
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<jernej>
wens: Isn't CONFIG_ARMV7_SECURE_BASE defined in sun6i.h to SUNXI_SRAM_B_BASE?
<jernej>
I don't see any guards
<jernej>
but you're right, SRAM B doesn't exist for H3
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<MoeIcenowy>
jernej: so dual head will fail on A64?
<MoeIcenowy>
(Although tcon0 may go through pll-mipi
<jernej>
It seems MIPI DSI and HDMI can't work at the same time
<jernej>
although I'm not sure what timing constrains are for MIPI DSI
<jernej>
MoeIcenowy: ^
<jernej>
and TCON1 can be clocked from PLL_VIDEO1
<anarsoul>
jernej: yeah, I couldn't get mipi dsi and hdmi working at the same time
<anarsoul>
I'm not sure why though
<jernej>
anarsoul: HDMI can't be clocked from TCON1, it seems
<jernej>
even if you change parent
<jernej>
it still considers only PLL_VIDEO0
<jernej>
eh, sorry, HDMI can't be clocked from PLL_VIDEO1
<jernej>
anarsoul: Has MIPI DSI any kind of dotclock which has to match to monitor resolution?
<anarsoul>
jernej: I don't remember
<anarsoul>
jernej: mipi dsi has dphy clock that has to be some specific value
<anarsoul>
but I don't remember what is its input
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