Turl changed the topic of #linux-sunxi to: Allwinner/sunxi /development discussion - did you try looking at our wiki? https://linux-sunxi.org - Don't ask to ask. Just ask and wait! - https://github.com/linux-sunxi/ - Logs at http://irclog.whitequark.org/linux-sunxi
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<KotCzarny> smaeul: hrm, i haven't tested running it from mainline kernel
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<KotCzarny> since i'm using devmem to map regs access it might have been stopped
<smaeul> KotCzarny: but doesn't legacy kernel use the arisc? so you'd be overwriting AW's blob with yours?
<KotCzarny> smaeul: it does, but i'm asserting reset before populating sram a2
<KotCzarny> then writing arisc ram contents then de-asserting reset
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<KotCzarny> since it's function is emulating power-off, i dont have to care about keeping previous ram/sram contents
<smaeul> right. maybe you're depending on some previous state that's not there with mainline, or maybe it's a hardware difference. If you release source, I could hack on it
<KotCzarny> will have to tidy up it before creating github repo, but i can give you tarbal in a few
<smaeul> no rush
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<KotCzarny> i'm compiling it on 2 machines because i dont have arm buildroot installed, so i compile arisc part on my x86-64 vm, then build arm static binary on my banana
<KotCzarny> in main dir you have normal make, but probably will have to update openrisc compiler path
<KotCzarny> you can then load fw directly via uboot or any favourite 0x40000 writing method
<KotCzarny> can you check if you have devmem enabled in kernel?
<KotCzarny> there is also a chance mainline kernel simply doesnt powerup arisc by default
<smaeul> the only thing you have to do to power up arisc is take it out of reset, so if you're doing that it should work
<KotCzarny> yup
<KotCzarny> i've added adding more verbosity for errors in arm loader to my todo
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<icenowy[m]> montjoie: Ethernet on a SoPine w/ Baseboard doesn't work at current linux-next
<icenowy[m]> "dwmac-sun8i 1c30000.ethernet eth0: Could not attach to PHY\ndwmac-sun8i 1c30000.ethernet eth0: stmmac_open: Cannot attach to PHY (error: -19)"
<icenowy[m]> the content of /sys/bus/mdio_bus/devices/stmmac-0:01/phy_id is 0x001cc915, which should be correct for RTL8211E, right?
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<icenowy[m]> sorry, old device tree used, please ignore it
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<pgreco> icenowy[m]: About the r40 usb patch that got lost
<pgreco> do you need to resend it? how can I help?
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<Hauke> Hi, I would like to boot a Linux imgae on a H3 from SPI flash
<pgreco> This is the one I mean https://patchwork.kernel.org/patch/9991711/
<Hauke> loading u-boot from SPI flash works, but it looks like there is still something missing to load Linux from SPI flash
<icenowy[m]> pgreco: PHY one?
<Hauke> do I need this patch: https://lists.denx.de/pipermail/u-boot/2017-February/281946.html with some optimisations?
<icenowy[m]> I just sent a mail to ask this
<pgreco> icenowy[m]: Great
<pgreco> should it be going into 4.15 as well?
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<beeble> Hauke: be more specific? what fails when you try to load the kernel?
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<Wizzup> Hauke: there is a more recent patch
<icenowy[m]> pgreco: no
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<icenowy[m]> this patch is not worthy to add during rc
<Wizzup> Hauke: I have not tested that patch but it's very close to our original patch, so it should work
<icenowy[m]> maybe even not 4.16 because of new year
<Wizzup> Hauke: you can then just load linux with the usual spi flash commands
<wens> linux-next hasn't been updated since 12/22... so much for testing newly merged patches :/
<icenowy[m]> wens: you can update sunxi-next ;-)
<icenowy[m]> P.S. could you check the H6 PR of sunxi-tools again? I updated it
<wens> I did this afternoon, but sunxi-next doesn't get automatic test coverage from kernel-ci
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<wens> i.e. people need to test it :)
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<pgreco> how long does it take for you to build a kernel?
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<Wizzup> Hauke: Please let me know if it works for you
<Wizzup> I will get a chance to test it in a few days
<icenowy[m]> pgreco: depending on config
<pgreco> icenowy[m]: Generally I rebuild fedora rpms for my test devices (bpi-m1, bpi-m2u, bpi-m3), with fedora default config
<pgreco> and it takes more than 8 hours. Maybe it is time to for a new laptop, :D
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<wens> pgreco: sunxi_defconfig + some bunch of wifi / ethernet phy drivers, with 8 cores and ccache, doesn't take more than a few hours
<wens> s/hours/minutes
<beeble> real 1m28.048s
<beeble> but yes, ccache
<pgreco> so I need to work more, and buy less
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<wens> you need to use ccache :)
<smaeul> on my desktop (2-4 cores, no ccache), I'd say about 10 minutes for a fully-featured yet sunxi-specific linux build, 1 minute for u-boot
<beeble> and have your ccache cache dir point to a ssd. otherwise you get i/o bound
<pgreco> yeah, so I need to really work on updating my build environment
<smaeul> and 1 second for atf :P
<pgreco> my main drive is ssd, but the one where de vm sits is an old 5400 1TB
<pgreco> so nothing is really helping my cause....
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<wens> yeah, compiling is half i/o bound
<Hauke> Wizzup: I haven't tried the patch yet, I tried it with unmodified uboot first and was unable to find the commands and later found this patch in the internet, I am new to uboot
<Hauke> I will try this later today or tomorrow
<Hauke> I would like to operate the orange pi r1 woth Openwrt / LEDE without a SD card
<Hauke> with that patch it is probably just putting all the parts together
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<Wizzup> Hauke: unmodified u-boot doesn't support spi on allwinner
<Wizzup> it can be loaded from it using spl, but u-boot itself cannot do anything without the patch I linked
<Hauke> Wizzup: ok thanks that explains why it did not work ;-), I assume that it should work with the patch you linked?
<Wizzup> yes, but you will need to change the u-boot dts of your orange pi
<Wizzup> see the second patch that changes the lime2 dts
<Wizzup> I have a lime2 prototype with spi flash, will try with it once I get back at work office
<Hauke> Wizzup: ok thanks
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<rasp> shouldn't give a mmap with length 0x218 and 0x1c20800 as offset give acces to the gpio registers instead of an EINVAL ?
<rasp> oh, on a v40
<icenowy[m]> why do you directly access the GPIO registers
<beeble> and shouldn't offset be page size aligned?
<beeble> but yeah, the bigger question is why you would access the registers directly
<rasp> well I'm just trying to understand these registers, that's basically all to it.
<rasp> According to the v40 pdf last register is at base+0x218...
<rasp> And it seems either being stuck to a 3.10 kernel or a 4.x without workings drivers thats the only way to do it.
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<beeble> if you just want to poke around these registers use devmem2 to save you some time
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<rasp> arrm, how would you set PI18 to input and then read PI(18) using devmem2 (address/type/data[to be written]) ?
<KotCzarny> you need proper registers to do that
<rasp> thats why I started with the mmap, devmem was suggested by beeble...
<KotCzarny> if you want to look how things are done you can check gpio.c in h3-shutdown-handler
<buZz> a/wg 202
<icenowy[m]> rasp: I suggest you to use sysfs
<icenowy[m]> if you want to do register ops I suggest you to do it in U-Boot
<KotCzarny> icenowy: is v40 supported?
<icenowy[m]> V40 = R40
<rasp> sysfs is really slow.
<rasp> icenowy: u-boot ?
<KotCzarny> icenowy: i've found that using arisc as dedicated microcontroller is great
<beeble> rasp: what are you trying to achieve at the end. we could suggest better solution if we understand what you are trying to do
<beeble> instead of sysfs you can also use the new gpio character device in mainline
<beeble> that would be faster in some cases or at least you can access multiple pins in a single command
<rasp> beeble: direct access to pins is what I'm looking for (as fast as possible regardless of os version) [it's not a matter of live or death, but would be nice]
<beeble> in 3.x you only have sysfs as standardized way of gpio user access. 4.8 introduced the new gpio abi as a character device and deprecated sysfs. if you want to bypass everything you will have to use /dev/mem if you don't plan to write your own driver
<beeble> even if i think there wouldn't be any real benefit to it against the gpio char device
<beeble> if you really want yo use /dev/mem (which i highly discourage) take a look at https://elinux.org/EBC_Exercise_11b_gpio_via_mmap
<KotCzarny> beeble: why is /dev/mem discouraged?
<KotCzarny> (for gpio/regs access)
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<beeble> KotCzarny: you have to run it as root? you can write arbitrary memory locations? you don't have any abstraction and have to reimplemnt everything for any soc?
<beeble> it's a dirty hack
<rasp> ok 3.10 is what thesse BPI people are offering, I've build and booted 4.15-rcx but can't get any gmac to work (usb neither althougs the dts suggests it should work)
<KotCzarny> isnt abstraction adding delays?
<rasp> so I'm trying to acces gpio directly, it's for that soc only anyway...
<beeble> KotCzarny: your gpio pin isn't as fast as your cpu core
<KotCzarny> how fast is gpio? half of the clock it uses?
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<beeble> and if you want low latency you shouln't run it from userspace in standard linux either
<rasp> that elinux example is exactly what I'm trying to do, except mmap() fails in the first place, which gets me back to square 1 ...
<KotCzarny> you have to do mmap at 4k align
<KotCzarny> what is your mmap command?
<rasp> align the address, or size ?
<KotCzarny> (also, if you just want to play, get devmem2.c)
<KotCzarny> address
<KotCzarny> and size is 4k in that example, havent checked other sizes
<beeble> KotCzarny: sysconf(_SC_PAGE_SIZE) for linux
<KotCzarny> recently i've had lots of fun programming on arisc
<rasp> ah, so the base of 0x1c20800 is the problem, you say ?
<KotCzarny> yes, see devmem2.c as a hint
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<rasp> yes thank's I already have devmem2.c here, that sheds some light :-)
<rasp> maybe some reading beforehand would have been right, sorry, thanks anyway :-)
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<icenowy[m]> interesting the DRAM controller/phy on H6 are both similar to the ones in Zynq UltraScale+
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<beeble> icenowy[m]: since allwinner used designware ip for pretty much all their ddr controller it's not that suprising?
<miasma> hm the h5 pages in the wiki still claim that the boards are unsupported..
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<icenowy[m]> beeble: yes it's not so suprising.
<jernej> icenowy[m]: so it shouldn't be so hard to implement DRAM init for H6?
<icenowy[m]> still hard
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<jernej> are you working on it?
<icenowy[m]> trying to work on it
<pgreco> rasp, have you tried booting with iomem=relaxed?
<pgreco> i've had problems using gpio without that option, mmap failed on certain options...
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<KotCzarny> hrm, anyone knows out of their heads what driver is needed on host when device is using g_ncm ?
<KotCzarny> Bus 001 Device 072: ID 0525:a4a1 Netchip Technology, Inc. Linux-USB Ethernet Gadget
<beeble> USB_NET_CDC_NCM
<KotCzarny> ty
<montjoie> yeah finaly got my H5 running (and crypto engine on it)
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<montjoie> wens: since I need two compatible for H3/H5, can I override &ccrypto {compatible =""} in h5 node ?
<montjoie> "can" in term of standard
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<rasp> pgreco: it's ok now, problem was alignment...
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<KotCzarny> hmm, is there H5 datasheet with registers list?
<KotCzarny> ahm, it's called 'h5 user manual'
<montjoie> yeah, datasheet are not real datasheet:)
<KotCzarny> hrm
<KotCzarny> maximum size 16MB
<KotCzarny> can someone upload that 23MB pdf to the wiki?
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<icenowy[m]> montjoie: I think it's ok
<icenowy[m]> or you can use the way I used in sunxi-h3-h5.dtsi
<montjoie> icenowy[m]: the base is in sunxi-h3-h5.dtsi
<montjoie> just I override the comaptible in sun50i-h5.dtsi
<KotCzarny> who has wiki admin rights?
<KotCzarny> nitehawk: plaes: ?
<plaes> o/
<plaes> just in time :D
<plaes> ah.. I do not have permissions to do that...
<KotCzarny> do you know who has?
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<icenowy[m]> montjoie: a usual method is have no compatible in sunxi-h3-h5.dtsi
<icenowy[m]> and have compatible in sun8i-h3.dtsi and sun50i-h5.dtsi
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<Hauke> Is a sync between the u-boot and the Linux kernel dts files planned in the near future?
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<smaeul> re-compressed version is much smaller :)
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