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<
icenowy[m] >
brought up USB3 of H6 on mainline kernel
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<
KotCzarny >
seems there is hack tool based on h3
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<
KotCzarny >
interestingly it uses nand?
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<
KotCzarny >
and i've thought there is no nand with h3
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<
KotCzarny >
unless they treat spi as nand
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<
icenowy[m] >
where's the nand?
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<
KotCzarny >
as i've said, seems they might use spi and some mtd driver to present it as /dev/nandX
10:06
<
icenowy[m] >
I think this page is just a mess
10:06
<
icenowy[m] >
see the DRAM part
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<
icenowy[m] >
it's copied from V3s.
10:06
<
KotCzarny >
otoh, there is nand_clk in the pdf
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<
KotCzarny >
btw. i've also found another way to pass params, because i'm going to write static arm binary with arisc payload to execute, i can just use command line to pass params (button, ir code etc)
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<
icenowy[m] >
It's V3s that do not have NAND controller at all
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<
KotCzarny >
interestingly it passes 768mhz mem test
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<
icenowy[m] >
I'm doubting the xhci on H6 is dwc3
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<
KotCzarny >
maybe customized/obfuscated?
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<
icenowy[m] >
not obfuscated at all
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<
icenowy[m] >
just aw wrote another driver
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<
icenowy[m] >
the register bit name is even the same
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<
icenowy[m] >
so it should be dwc3 bound with a custom phy
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<
icenowy[m] >
wink confirmed it's dwc3
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<
KotCzarny >
hmm, is writing to sram a2 on h3 possible with /dev/mem from linux side?
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