ChanServ changed the topic of #linux-rockchip to: Rockchip development discussion | IRC log http://irclog.whitequark.org/linux-rockchip | Community GH https://github.com/linux-rockchip | Rockchip GH https://github.com/rockchip-linux | ML https://groups.google.com/group/linux-rockchip
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<micken> SIgh None of the sustem interrupts is fireing accordning to GIC :(
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<beeble> tkaiser: https://gist.github.com/kgoger/d6a45aefca64c80205eac32586fbb34c iozone looks like it is more cpu dependent as fio. so there are two runs, one running on all cores, the second only on the a72
<maz> micken: can you please explain what you're trying to do? you give no indication of whether you're running bare metal or as part of the kernel, and the GIC configuration is not exactly trivial...
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<beeble> maz: he is porting risc os
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<maz> beeble: right. at last explaining which GIC version, how is the kernel booted (secure, non-secure), how is the GIC distributor setup (groups, priorities), how the CPU interface is configured...
<maz> beeble: you need to know all of that in order to answer the "why isn't my interrupt delivered" question.
<maz> s/last/least/
<beeble> maz: i was just answering the part of "bare metal" :)
<beeble> have nothing to do with it at all
<maz> beeble: I know! ;-) the rest of the rant is directed at micken...
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<tkaiser> beeble: Thank you for the numbers. In case the board is still running contents of /proc/interrupts would be interesting too :)
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<tkaiser> beeble: I used your numbers now for my '2018 single board computer storage performance overview': https://forum.armbian.com/topic/1925-some-storage-benchmarks-on-sbcs/?do=findComment&comment=51350
<beeble> whee, biggest peni^Wnumbers
<tkaiser> Exactly ;)
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<tkaiser> beeble: BTW: what does /sys/module/pcie_aspm/parameters/policy tell? Is it powersave or performance?
<beeble> ah you also asked for interrupts
<beeble> give me a sec
<beeble> haha great
<beeble> [default]
<beeble> whatever that is
<beeble> (have not checked the source)
<tkaiser> Could make a hufe difference with small blocksizes.
<beeble> "Use the BIOS defaults for PCI Express ASPM"
<beeble> let's try to change it
<tkaiser> With the 4.4 RK kernel it should be adjustable through sysfs
<beeble> i run the tests with mainline
<tkaiser> Ah
<beeble> https://gist.github.com/kgoger/768e987eca09fdb9c02a85819e704122 /proc/interrupts fresh after a reboot + one iozone run on the a72s
<tkaiser> NVMe is nice. IRQ affinity works automagically :)
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<beeble> tkaiser: not really a significant difference between performance and powersafe (single testrun)
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<tkaiser> Ok, thank you :)
<beeble> you are welcome
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<micken> maz: Sorry SSH died. Ok Here goes a lenghty version. As beeble told you I am porting riscos to RK3288 using a tinker-board. I have setup the GIC according to the documentation. We already have driver for it for other socs, so my work have been just checking it. I have also compared it with u-boot. Everything seems to be in order, but apperantly something isn't. My recent tests (last hours) makes me think that hardware device interrupts , for
<micken> maz: Here is our GIC driver for OMAP5 , which is the one I am working with: https://www.riscosopen.org/viewer/view/castle/RiscOS/Sources/HAL/OMAP5/s/Interrupts?rev=1.2.2.1;content-type=text%2Fplain
<maz> micken: do you boot secure or non-secure?
<micken> maz: non-secure
<maz> micken: how do you switch from S to NS? do you have any setup code that runs in S before the switch?
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<micken> maz: perhaps I have misunderstood what secure means in this context. When I ahve been reading I thought of secure as in TZ..!
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<micken> maz: I boot from u-boot, just launching my kernel (osrom).
<maz> micken: TZ is a product (and/or a software spec). Secure is the mode TZ runs in, but that's also the mode the CPU starts in. the GIC can deal with both secure and non-secure interrupts, and must be configured accordingly.
<micken> maz: does u-boot leave me in secure ?
<maz> micken: only you can know that.
<micken> ok
<maz> micken: you need to see if your u-boot version is configured to switch to NS.
<micken> maz: ok, I can dig into u-boot a bit more then.. But if I am in secure-mode it can explain a few things
<maz> micken: secure is actually easier. there is no priority shift and other PMR madness that happens in NS.
<micken> hmm
<maz> micken: but that omap5 code is... wow... from another era.... ;-)
<micken> maz: thanks a lot for the hint.. might prove very usefull
<maz> micken: no worries. might be easier on email though.
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<micken> maz: I "think" it is running non-secure. It is a little emabarrasing , but I don't have anything (well...) that can build u-boot. As far from what I can see secure is optional. And I tried to switch to non-secure (resulted in complete halt)
<micken> maz: and I am using non secure GRF
<micken> gah need to find a linux box
<micken> perhaps I can use the tinkerboard!
<beeble> virtualbox to the rescue?
<micken> :/
<micken> ah yes vbox
<micken> might do the trick
<micken> But a better way would be if I could dd from windows and build in the "linux" mode thingy , didn't think of that
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