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<LongChair>
stdint: morning, i'd have a few questions regarding drm if you have a min
<stdint>
ok
<LongChair>
ok first question is about vsync. the layer we add with drmModeAddFB2 that contains the frame. is it displayed when the function is called of after vsync ?
<LongChair>
because it seemed that i couldn't use teh pageflip function on the fbid which is created by drmModeAddFB2
<LongChair>
and depending on when that layer is displayed, you would need to call that function either before vsync or just right after it
<LongChair>
and i have foudn really very little doc on the DRM API for userland
<LongChair>
stdint: see what i mean ?
<stdint>
LongChair, yes I want to implement pageflip function, but I have the same question
<stdint>
lacks of document, I don't know the function could improve the performance
<stdint>
you must wait the event
<stdint>
you could read kmssink in gstreamer
<LongChair>
i already did
<stdint>
drmModeSetPlane() is the real function that put the buffer into screen
<stdint>
drmModeAddFB2 just import the external buffer(even it is not) from outside
<LongChair>
ok
<LongChair>
so there is no way to have the buffer prepared and get it displayed when the page is flipped ?
<stdint>
you could import them before using drmModeAddFB2
<stdint>
but not much help actually
<LongChair>
yeah usually with drm you would use "dumb" buffers, and you coudl page flip on those
<LongChair>
which would make buffer switching perfect
<stdint>
page flip have nothing to do with dumb buffer
<stdint>
it is the driver level problem
<stdint>
the mpp create buffer in the same way as create dumb buffer
<stdint>
creating dumb buffer
<LongChair>
drmModePageFlip allows to pas a dunb buffer id to which you want to flip
<LongChair>
so if you create 2 dumb buffers, you can draw to one offscreen, and then flip on vsync
<LongChair>
because drmmodepageflip will accept that dumb buffer id
<LongChair>
stdint: but it doesn't seem to accept the buffer id returned by drmModeAddFB2
<stdint>
I see how does the drmmodepageflip work, but I didn't see many driver have implemented that
<LongChair>
mpv does
<LongChair>
I got it changed a bit to handle rockchip
<stdint>
no, I mean the kernel driver
<LongChair>
ah
<LongChair>
stdint: because even in gst code, we do drmModeAddFB2 , then drmModeSetPlane, and then wait vsync
<LongChair>
if the layer is shown on teh drmModeSetPlane, then it means that the display timing is pretty bad
<LongChair>
ok i'll make some more experimentation then
<LongChair>
now i had a second question :)
<LongChair>
when i get typically a 4K image (3840 x 2160)
<LongChair>
and have a 1920x1080p display
<LongChair>
it seems that the drmModeSetPlane requires at least the dest with and height to be aligned on 16
<LongChair>
and typically 1080 isn't aligned on 16
<stdint>
I am not sure whether the VOP has this limit
<stdint>
but the vpu does
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<LongChair>
stdint: i had artefacts when not aligning it
<LongChair>
and it's not very nice, because, i needed to display the 1080p image o a 1072 or 1088 area .. so causes soem stretching
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<stdint>
it is not a big deal, what you need to do is set the width to original width but stride to aligned stride
<LongChair>
where ?
<LongChair>
because when i'm decoding a 2160p image it's no problem
<LongChair>
2160 is 16 aligned
<LongChair>
so i get that 2160 buffer and want to display on a 1080p display
<LongChair>
at that time i have no option to fiddle with aligned heights
<stdint>
stride is set in drmModeAddFB2()
<stdint>
drmModeSetPlane would set the dest width and src width
<LongChair>
the thing is that in drmModeAddFB2, both height and with are 16 bytes aligned as i have 3840x2160 there
<LongChair>
but drmModeSetPlane would then do the 1080p scaling
<stdint>
I don't meet this problem
<LongChair>
so i would do something like drmModeSetPlane(.... 0,0,3840,2160, 0 << 16, 0, << 16, 1920 << 16, 1080 << 16 )
<LongChair>
and if the dest hieght is not 16 byes aligned .. i have artefacts on teh few first and few last lines
<LongChair>
will fix if i replace 1080 with 1072 or 1088
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<olerem>
hallo all, i'm looking for information about availability of rockchip SoCs. Do this company provides long term support?
<mrjay>
mmind00: i think it's a problem with unpacking ramdisk ... it might be a kernel issue or uboot issue
<holin>
hi, would anyone here happen to know whether mainline kernel can be run on ASUS Chrombook C100 (Flip) with the google bootloader (not libreboot)? When I try anything else than chromium 3.14 kernel I only get a black screen and either the machine powers off or gets seemingly stuck.
<holin>
chromium 3.14 would be fine, too, if i found a combination of mali / vpu drivers that would work with it and give acceleration under X11
<LongChair>
ayaka: also does the miniarm branch had the vpu-service ?
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<beeno>
mac-l1, are you here?
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<beeno>
Can anyone tell me where I can find the best content/docs for the vpu-api
<phh>
which one? :D
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<beeno>
phh, you answering me? I'm looking at <rockchip/vpu_api.h> and macffplay source
<LongWork>
beeno: i owuldn't expect too much docs :) there are a few API which are more self explanatory though
<LongWork>
phh: seems like i got ffmpeg / mpv work together not too bad with drm / dmabuf
<LongWork>
still need to solve the overlay issue
<phh>
LongWork: yup i've read, that's cool
<phh>
erm, I need my subtitles :P
<phh>
LongWork: though I still don't have a proper kernel with vpu working
<LongWork>
i used the 4.4-release
<LongWork>
but i should give a try to the minarm branch
<phh>
I have no board which works out of the box with 4.4
<LongWork>
ah
<LongWork>
4K doesn't seem very well supported in terms of display though
<phh>
well, wzyy2 did mention that rga is needed for 4k rendering
<LongWork>
i still can't make sure that my stuff works right with a real 4K display mode as i can't propery switch to it
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<LongWork>
i suppose rga should be underlying the drm API ...
<LongWork>
redering 4K video in a 1080p mode works ... but soem dragons could show up when using a 4K mode
<beeno>
Is the following command necessary or is it optional for performance reasons --> ctx->control(vpu_ctx,VPU_API_SET_VPUMEM_CONTEXT,(void*)vpu_display_pool);
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