01:08
<
naobsd >
hmmm what's ARMv8 Crypto Extensions?
01:08
<
naobsd >
Error: selected processor does not support `aese v0.16b,v2.16b'
01:13
<
naobsd >
gcc -march needs +crypto, but I guess rk3368 doesn't support it
01:13
<
naobsd >
lets disable CE support in .config...
01:29
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01:59
<
naobsd >
Features: fp asimd evtstrm aes pmull sha1 sha2 crc32
01:59
<
naobsd >
in /proc/cpuinfo
01:59
<
naobsd >
so it should be supported...?
02:00
<
naobsd >
btw arch/arm64/kernel/asm-offsets.s compile error is not in next-20151208
02:00
<
naobsd >
but there are many commits between 1208..1209
02:02
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02:02
<
naobsd >
about armv8 crypto
02:02
<
naobsd >
CFLAGS_aes-ce-cipher.o += -march=armv8-a+crypto
02:03
<
naobsd >
hmm why my compiler failed...
02:09
<
naobsd >
test.c is compilable and no crash
02:09
<
naobsd >
-march=armv8-a+crypto should be ok...
02:21
<
naobsd >
it seems -mgeneral-regs-only disables +crypto...
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06:33
<
naobsd >
next-20151208 is almost fine on both arm(firefly) and arm64(orion r68)
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07:43
<
xming_ >
mmind00: 64GB sdxc boots fine too with increased strength
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08:16
<
mmind00 >
xming_: \o/ great
08:23
<
xming_ >
mmind00: do you have any clues how to get full 4GB?
08:26
<
mmind00 >
xming_: uboot is definitly not my thing ... I'm even lacking behind trying to actually test mainline uboot
08:27
<
sjoerd >
mmind00: pfff :)
08:28
<
mmind00 >
sjoerd: :-P
08:28
<
sjoerd >
xming_: given the u-boot code for memory setup came from coreboot probably best to check there how it handles boards with different memory sizes
08:28
<
sjoerd >
or at least i assume there are rk chromebooks with 4G
08:28
<
xming_ >
sjoerd: you told me try changing dtb, so it's uboot's dtb?
08:29
<
xming_ >
I only have to look uboot related right? Not kernel stuggs
08:29
<
xming_ >
/stuggs/stuffs
08:30
<
sjoerd >
Right, if u-boot setups and recognize 4G it should adjust the dtb as passed to the kernel with the right memory size
08:36
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08:39
<
xming_ >
google says Asus C201 uses rk3288 and has 4GB option
08:42
<
sjoerd >
Right so i'd look at its coreboot code and see what it does compared with u-boot
08:42
<
sjoerd >
I really don't know the memory setup section too well either and i don't have documentation for the phy which makes everyting a bit limited to, check what known working code does :)
08:47
<
xming_ >
so libreboot is the x86 style BIOS/UEFI hacked with emmc/nand support?
08:47
<
xming_ >
forked from coreboot?
08:49
<
sjoerd >
No chromeos uses coreboot
08:49
<
sjoerd >
which is why i'm pointing at that
08:49
<
sjoerd >
i'm not sure about libreboot tbh
08:52
<
xming_ >
Libreboot was established as a distribution of coreboot without proprietary binary blobs
08:53
<
xming_ >
c201 is supported in libreboot, I think I need that
08:53
<
xming_ >
without blob init stuffs
08:53
<
sjoerd >
feel free to look at that, whatever gives you the answers really
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08:55
<
naobsd >
what happen if we use ddr blob with mainline u-boot
08:56
<
naobsd >
with proper "load from mask rom" support
09:00
<
sjoerd >
naobsd: things get quite confused
09:01
<
sjoerd >
the ddr blob sets up stuff differently
09:01
<
sjoerd >
I tried that and then u-boot thought there was only 64M ram
09:01
<
sjoerd >
no clue why
09:03
<
xming_ >
what a weird tree
09:05
<
naobsd >
rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf>;
09:05
<
naobsd >
this should be 1GB
09:05
<
naobsd >
I'm not sure this values are not changed or updated while probing
09:08
<
xming_ >
ah coreboot look much better
09:09
<
naobsd >
ddr blob tells those values, but I cannot refer it for now...
09:12
<
sjoerd >
naobsd: right 1G, 2 channels
09:13
<
naobsd >
so rockchip,sdram-channel should be modified for 4GB
09:13
<
naobsd >
I cannot find any code which updates those values
09:13
<
sjoerd >
4G ram is 2x2G
09:13
<
xming_ >
does firely use DDR3 or LPDDR?
09:13
<
naobsd >
what I said is, those values need to be updated as 2GB for 4GB board
09:14
<
naobsd >
DDR blob prints right values on boot
09:14
<
naobsd >
I don't have it for now
09:14
<
naobsd >
col might be +1
09:17
<
xming_ >
blobk uboot output
09:19
<
xming_ >
ah missed the lines before
09:19
<
xming_ >
Channel a: DDR3 200MHz
09:19
<
xming_ >
Bus Width=32 Col=10 Bank=8 Row=15 CS=2 Die Bus-Width=16 Size=2048MB
09:19
<
xming_ >
Channel b: DDR3 200MHz
09:19
<
xming_ >
Bus Width=32 Col=10 Bank=8 Row=15 CS=2 Die Bus-Width=16 Size=2048MB
09:20
<
naobsd >
CS value is different but I'm not sure which one in rockchip,sdram-channel
09:20
<
xming_ >
does the 2GB version also use 2 channels?
09:24
<
xming_ >
only CS is different
09:24
<
xming_ >
CS == counts ?
09:24
<
sjoerd >
worth bumping rank to 2 to see if that does the right thing indeed
09:25
<
sjoerd >
you select chips from diffrent ranks using CS (chip select)
09:25
<
sjoerd >
would be interesting to know how the blob figures that kind of stuff out though
09:27
<
naobsd >
I assume ram info on pmu reg is compatible
09:27
<
naobsd >
READ_CS_INFO(ch) ((((pPMU_Reg->PMU_PMU_SYS_REG[2])>>(11+(ch)*16))&0x1)+1)
09:27
<
naobsd >
SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16)
09:28
<
naobsd >
same ddr blob can be used for both 2GB board and 4GB board, it should bedetected at run time
09:29
<
sjoerd >
naobsd: oh intersting, i didn't know the code was available
09:30
<
naobsd >
ddr code is available in RK 3.0/3.10 kernel tree
09:31
<
xming_ >
rank = sdram_params->ch[channel].rank | 2;
09:31
<
naobsd >
rockchip,sdram-channel = /bits/ 8 <0x2 0xa 0x3 0x2 0x1 0x0 0xf 0xf>;
09:32
<
naobsd >
then 0x2 becomes 3...
09:32
<
naobsd >
"| 2" is not good if you use sdram-channel = /bits/ 8 <0x1 ...
09:33
<
naobsd >
I recommend "rank = 2;" for now
09:33
<
naobsd >
ah, if all code refers rank as like as "if (rank > 1)" then 3 is ok ;)
09:34
<
naobsd >
oops, there are several "rank | 1"
09:35
<
xming_ >
so, should I change the dtb to 'rockchip,sdram-channel = /bits/ 8 <0x2 0xa 0x3 0x2 0x1 0x0 0xf 0xf>'
09:35
<
xming_ >
or change the code to 'rank = 2;'
09:35
<
naobsd >
probably it's not so simple
09:35
<
xming_ >
as long as it doesn't brick my firefly I don't mind to try
09:37
<
naobsd >
it's complicated for me
09:37
<
xming_ >
it's almost gibberish to me
09:37
<
naobsd >
all I can do is just try ;)
09:41
<
naobsd >
it seems rank is bitmap, not value
09:41
<
naobsd >
rockchip,sdram-channel = /bits/ 8 <0x2 0xa 0x3 0x2 0x1 0x0 0xf 0xf>;
09:41
<
naobsd >
and code unchanged ("rank | 1" -> 3) might work
09:43
<
xming_ >
650 * CS0, n=1
09:43
<
xming_ >
651 * CS1, n=2
09:43
<
xming_ >
652 * CS0 & CS1, n = 3
09:43
<
xming_ >
looks promising
09:46
<
naobsd >
melt my brain
09:47
<
xming_ >
Model: Firefly-RK3288
09:47
<
xming_ >
DRAM: 0 Bytes
09:48
<
naobsd >
4GiB is 0 of course
09:48
<
naobsd >
ah sorry unit is MiB in code
09:49
<
naobsd >
something didn't work properly with rank 2 ;)
09:50
<
naobsd >
priv->info.size = sdram_size_mb(priv->pmu) << 20;
09:51
<
naobsd >
arch/arm/include/asm/types.h:typedef unsigned long phys_addr_t;
09:53
* xming_
waits for the clue :p
09:53
<
naobsd >
size_mb = min(size_mb, 0xff000000 >> 20);
09:53
<
naobsd >
sdram_size_mb() should return 4GiB-16MiB ?
09:54
<
naobsd >
(4GiB - 16MiB) >> 20
09:54
<
naobsd >
then "priv->info.size = sdram_size_mb(priv->pmu) << 20;" should be fine :(
09:55
<
naobsd >
confusing...
09:57
<
naobsd >
well melted brain here
10:10
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10:10
<
xming_ >
that part is straight from coreboot
10:13
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10:15
<
naobsd >
need more investigation :(
10:20
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10:36
<
xming_ >
blah I need the google's fork of coreboot, not the original one
10:37
<
xming_ >
still not getting those SoCs
10:39
<
xming_ >
finally found them
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11:58
<
naobsd >
./arch/arm/cpu/armv7/sunxi/dram_sun6i.c ./arch/arm/include/asm/arch-sunxi/dram_sun6i.h should be read
12:09
<
naobsd >
ah maybe netbsd code just read result of configuration...
12:10
<
naobsd >
sun6i sunxi_dram_init() try
12:11
<
naobsd >
arch/arm/cpu/armv7/sunxi/dram_helpers.c::mctl_mem_matches()
12:14
<
naobsd >
saopdfj;owharg
12:21
<
naobsd >
haduhlgaer
12:34
<
naobsd >
yo ho, yo ho,
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12:54
<
naobsd >
hmm, dram common registers in sun6i is no relation to us... :(
12:55
<
naobsd >
ctl/phy should be same
13:01
<
naobsd >
coreboot pistachio code is very straightforward
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13:07
<
xming_ >
chromos' coreboot fork has various veyron* platform
13:07
<
xming_ >
which is rk3288
13:07
<
xming_ >
most codes are very similar to uboot
13:08
<
xming_ >
I am following the trail DRAM_SIZE_MB, but can't see that they do much with it
13:12
<
naobsd >
sun6i runtime detection code is interesting
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19:38
<
amstan >
xming_: you want firmware-veyron-6588.B
19:39
<
xming_ >
amstan: is that different than the code in git?
19:39
<
amstan >
xming_: you can also ask jwerner over in #chromiumos for more details, he's been the main maintainer of that branch
19:39
<
amstan >
that's the branch that you want
19:39
<
xming_ >
amstan: ah thanks for the tip
19:39
<
amstan >
of wait.. you're looking at upstream coreboot?
19:40
<
xming_ >
no chromeos'
19:40
<
amstan >
that's what yo uwant
19:40
<
xming_ >
yeah I figured that out
19:40
<
xming_ >
thanks a lot
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