<azonenberg>
i think you end up getting the isolation diodes forward biased all the time :p
<azonenberg>
Unless i'm misunderstanding the question
<berndj>
azonenberg: no, i'd flip *everything*, including the well contacts
<azonenberg>
oh... hmm
<berndj>
i'd probably make the inverted section narrower than the rest of the cell, so the power rails could still go straight across, but a "private" rail for the inverted rails
<azonenberg>
hmm, sounds overcomplicated
<azonenberg>
maybe cheat and use poly as a routing layer? :p
<azonenberg>
Though you can't do that on a modern process
<azonenberg>
they usually do double patterning etc on poly
<berndj>
i wanted to try laying out that dff like that to see if it saves real estate compared to using jumpers to get gate signals to cross over each other
<azonenberg>
i see
<azonenberg>
What process node are you targeting?
<berndj>
magic calls it "scalable cmos"
<azonenberg>
So presumably relatively large?
<berndj>
but it's more polygon doodling and self-didactic than actually making something real
<azonenberg>
like 180nm or so?
<berndj>
probably
<azonenberg>
you can get away with lots of stuff at those levels that you could never do at 22nm
<berndj>
are you saying the design rules are overrestrictive considering modern processes?
<berndj>
i mean that, if you used a 22nm process to build a 180nm chip, you'd have the luxury of using 22nm rules, not the 180nm rules
<azonenberg>
luxury, lol
<azonenberg>
no
<azonenberg>
it probably wouldnt even pass DRC
<berndj>
but i thought the big processes were actually just all the old equipment, hence old rules
<azonenberg>
What i mean is, it's generally not possible to build a chip five gens old on a modern porcess
<azonenberg>
process*
<berndj>
*not possible*?
<azonenberg>
maybe if you retooled the masks or the process workflow a lot
<azonenberg>
TSMC 28nm for example uses double patterning
<berndj>
oh, you mean the same chip 5 times smaller?
<azonenberg>
Note that the gates are all exactly the same size and regularly spaced
<azonenberg>
The process cannot make a gate any bigger or smaller
<azonenberg>
(you're looking at poly and active)
<azonenberg>
TSMC 28nm
<azonenberg>
It's two litho steps, one for defining the parallel lines and then one for cutting them vertically
<azonenberg>
It wouldn't surprise me if the parallel lines are generated by some kind of interference pattern
<berndj>
i thought that's what "double patterning" is?
<berndj>
(interference magic)
<azonenberg>
Not strictly
<azonenberg>
There's a half dozen or soe forms of double patterning
<azonenberg>
I dont know exactly what they used here
<azonenberg>
Its possible this is actually triple litho
<azonenberg>
one double-patterning step for the lnies, then another for the cut
<azonenberg>
another single litho*
<azonenberg>
Anyway the point is, larger processes are generally less restrictive in terms of allowing arbitrary geometry that doesn't violate clearance or density rules
<azonenberg>
For example if you are not using copper damascene or CMP, you don't need fill patterns or uniform metal density
<berndj>
what's that about btw - not setting up unequal thermal stresses?
<azonenberg>
No
<azonenberg>
The problem is that copper and oxide polish at different rates
<azonenberg>
and you dont want sagging (since the pad isn't perfectly flat, it'll deform slightly if one area polishes faster than another and make the problem worse)
<azonenberg>
So you want uniform, roughly, metal density
<berndj>
interesting
<berndj>
so many weird things that happen
<berndj>
also: those power rails on micrographs have a continuous row of contacts; is this important or would it be (electrically) enough to have one or two contacts into a mini-well that's "wrong way round"?
<azonenberg>
Not sure if you need that many
<berndj>
hmm, so you can only have one width of poly in some processes?
<azonenberg>
Yeah
<azonenberg>
And it has to be axially aligned
<azonenberg>
and exactly the same size
<azonenberg>
pretty much uniform pattern
<azonenberg>
i'm not sure how much you're able to deviate from that
<berndj>
so no non-manhattan lines either?
<azonenberg>
Older chips did 45deg but i rarely if ever see them in modern devices
<azonenberg>
except in really large geometry like power buses
<azonenberg>
that may just be due to the autorouters though
<berndj>
i think i've done it
<berndj>
almost. i just have to squeeze in an m2 contact here
<berndj>
magic's drc won't let me put it on top of a poly contact though :(
<berndj>
"via must be on a flat surface" which is fair enough i guess