<sb0>
rjo, any guess about what causes a dds chip to misbehave in a way that writes to FTW, PTW, etc. read back correctly, whereas writes to CFRs are ignored (and CFR reads always return the default values from the datasheet)?
<sb0>
there is also no output
<cr1901_modern>
Interfacing to an old chip with a bidirectional data bus. I included a counter (greater-than/less-than) to test the switching speed of the FPGA's pin from in to out and back... 300,000 clock cycles at 50MHz o.0;
<cr1901_modern>
Is that normal?
<sb0>
sync_clk out is correct (generates 125MHz from the 3GHz input)
<sb0>
hm. i can switch sync_clk out on and off using CFR2 and FUD
<sb0>
so why are the other CFRs not working ...
<sb0>
ah. they need a FUD to update the readback value.
<GitHub116>
[artiq] sbourdeauducq pushed 2 new commits to master: http://git.io/vsg1Y
<GitHub116>
artiq/master 094fc1c Sebastien Bourdeauducq: qc2: DDS selection is active low
<GitHub9>
[artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/vsgyx
<GitHub9>
artiq/master d38f1e6 Sebastien Bourdeauducq: ad9xxx: fix gpio signal length
<sb0>
rjo, ok so the only remaining mystery is, why the DDS output stays at 0 even though register read/writes are OK and clocking seems fine as the DDS outputs the 125MHz correctly
<sb0>
sync_out is also missing
<sb0>
"Amplitude scale factor - This 12-bit word controls the DDS frequency"
<sb0>
the datasheet is great. also tells you to set bits that are documented as "reserved" a few pages before ...
<cr1901_modern>
Is there such thing as a GREAT datasheet?
<sb0>
the 1.8V supply current is also wrong. I'm measuring 138mA while it should be 400-450mA
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<GitHub193>
[misoc] enjoy-digital pushed 5 new commits to master: http://git.io/vs22x
<GitHub193>
misoc/master b8f3fd5 Florent Kermarrec: README: small update
<GitHub193>
misoc/master 158fbe4 Florent Kermarrec: sdram/phy/s6ddrphy: rename S6DDRPHY to S6HalfRateDDRPHY and use ORed wrdata_en/rddata_en (the controller already manages that)
<GitHub193>
misoc/master 8bb30a8 Florent Kermarrec: liteeth/phy: fix autodetect (clk_freq not necessary passed in kwargs)
<GitHub145>
[misoc] enjoy-digital pushed 1 new commit to master: http://git.io/vs2aQ
<GitHub145>
misoc/master a1e4183 Florent Kermarrec: sdram/phy/s6ddrphy: fix comment on S6QuarterRateDDRPHY
<GitHub2>
[artiq] sbourdeauducq pushed 4 new commits to master: http://git.io/vsaJt