02:15 <sb0> rjo, yes, that's for having >=32 P2P channels without an oversized/expensive FPGA (only the very high end ones have that many transceivers)

03:01 <cr1901> Well that's a problem. Home laptop should NOT be on right now...

05:45 <rjo> iirc the xc7k325t (kc705) has 24 transcievers.

05:46 <rjo> but if we run out of transcievers i would imagine that first the wiring (24 SFP cages will look like a mess) will become a mess. inventing distributed 1:8 "concentrators" would be what i would do then.

05:50 <sb0> aka white rabbit switches, no?

06:50 <GitHub173> [artiq] sbourdeauducq pushed 2 new commits to master: http://git.io/v3V9P

06:50 <GitHub173> artiq/master f073dfa Sebastien Bourdeauducq: ttl: add input/output doc

06:50 <GitHub173> artiq/master a1c7efd Sebastien Bourdeauducq: doc: use m-labs anaconda account

06:58 <GitHub57> [misoc] sbourdeauducq pushed 3 new commits to master: http://git.io/v3VHx

06:58 <GitHub57> misoc/master d00e774 Tim 'mithro' Ansell: All commands run should be checked.

06:58 <GitHub57> misoc/master eeda704 Tim 'mithro' Ansell: Use shell for globbing in clean.

06:58 <GitHub57> misoc/master d8fd4fe Tim 'mithro' Ansell: Use shutil rather then rm -rf command.

07:29 <travis-ci> m-labs/artiq#398 (master - a1c7efd : Sebastien Bourdeauducq): The build passed.

07:29 <travis-ci> Build details : https://travis-ci.org/m-labs/artiq/builds/75390292

08:10 <mithro> anyone on this channel at #cccamp15?

10:37 <GitHub112> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/v3reX

10:37 <GitHub112> artiq/master f2911d6 Sebastien Bourdeauducq: Enable TCP keepalive on the core device...

10:51 <sb0> ysionneau, pygit2 is still missing from the new anaconda repos

10:58 <ysionneau> uploading the remaining packages now

11:07 <ysionneau> should be ok now

11:07 <ysionneau> sb0: do you still want to switch to alabaster theme for the manual? it seems to be more "white" than the current one

11:08 <ysionneau> and I don't see a lot of possibility to tweak the bgcolors to keep some darkish theme

11:08 <sb0> no, that's not important

11:20 <travis-ci> m-labs/artiq#399 (master - f2911d6 : Sebastien Bourdeauducq): The build has errored.

11:20 <travis-ci> Build details : https://travis-ci.org/m-labs/artiq/builds/75415381

11:26 <GitHub33> [misoc] enjoy-digital pushed 1 new commit to master: http://git.io/v3rno

11:26 <GitHub33> misoc/master a9d40e7 Florent Kermarrec: tools/flterm.py: cleanup kernel-adr argument parsing

15:07 <ysionneau> https://github.com/libssh2/libssh2/blob/master/COPYING

15:07 <ysionneau> this website says it's BSD, but it's not clear to me why http://www.libssh2.org/libssh2-vs-libssh.html

16:51 <GitHub64> [artiq] fallen pushed 1 new commit to master: http://git.io/v3Kav

16:51 <GitHub64> artiq/master 1ce8bbe Yann Sionneau: conda: add recipe for libssh2 package

17:29 <travis-ci> m-labs/artiq#400 (master - 1ce8bbe : Yann Sionneau): The build has errored.

17:29 <travis-ci> Build details : https://travis-ci.org/m-labs/artiq/builds/75472731

18:10 <rjo> sb0: no. the hardware maybe but certainly not the gate and software.

18:11 <rjo> it would need to be as asymmetric as our master-slave design is. no switching, single master. the concentrators would only aggregate their slaves into one big slave.