sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
ylamarre has joined #m-labs
ylamarre has quit [Read error: No route to host]
ylamarre1 has joined #m-labs
ylamarre1 has quit [Quit: ylamarre1]
<rjo>
sb0__: how is an asynchronous FIFO supposed to behave if just one clock domain resets? doesn't that lead to invalid data showing up and/or valid data being overwritten?
<sb0__>
is that with the latest runtime?
<sb0__>
yes, you should reset both domains
<rjo>
i guess driving both resets (with MultiReg on one) with either the and or the or of the two clockdomain resets dependeing on the preferred behavior.
<rjo>
that is always with the current bitstream+bios+runtime.
<whitequark>
in essence, you're creating a new RPC call for every combination of strings, right?
<sb0__>
yes
<sb0__>
which is totally fine for the purpose of accessing certain results/parameters
<whitequark>
that makes sense
<whitequark>
sure. that can be done. I'd rather do it at codegen time though
<sb0__>
maybe, but when would that work, i.e. the current unit tests can be rewritten to use set_result("xxx",...) and function properly on the device?
sb0_ has joined #m-labs
<whitequark>
the unit tests currently go through LLVM anyway
<whitequark>
so, yes
sb0__ has quit [Ping timeout: 264 seconds]
<sb0_>
my question was more: if you want to implement that in your new codegen compiler (only), will it work sometime next week?
<whitequark>
I think so. SSA IR should be done by tomorrow already
<whitequark>
pipistrello tracking # not updated since 29th...
ylamarre has joined #m-labs
sb0_ has quit [Quit: Leaving]
<cr1901_modern>
seeedstudio took a month to ship me my CPLD board (which doesn't even fit on a breadboard properly), and they didn't update the status of it at any time...
sb0 has joined #m-labs
<GitHub120>
[artiq] whitequark pushed 5 new commits to new-py2llvm: http://git.io/vqA3V
<GitHub120>
artiq/new-py2llvm 4358c5c whitequark: Unbreak return type inference.
<GitHub120>
artiq/new-py2llvm 4785f0a whitequark: Don't error out in inferencer if builtin arguments have polymorphic types.
<whitequark>
whoa, I haven't pushed in a while
<sb0>
so you're doing the whole IR thing?
<sb0>
the flow would be AST -> IR -> transforms (interleave, inline, etc.) -> LLVM -> machine code?
<whitequark>
yes. inlining and interleaving the ASTs is insane
<sb0>
what's wrong with it?
<sb0>
you can unparse nicely
<whitequark>
you've encountered the problems with inlining yourself, haven't you?
<sb0>
that can be solved by adding goto
<whitequark>
it simply doesn't compose
<whitequark>
note that I'm not converting *everything* to an IR, expressions stay
<whitequark>
it's mostly a representation for control flow
<whitequark>
with AST inlining, you'd be doing the exact same thing, but in an error-prone ad-hoc way
<sb0>
is there a nice way to dump it for debugging?
<whitequark>
str(fn)
<whitequark>
well, not quite all code for that is in place, locations're missing
<whitequark>
but I expect it to be readable
<whitequark>
the SSA conversion here mainly involves lowering control flow and lexical scoping, both of which cause trouble when inlining and interleaving...