sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<rjo>
ysionneau, sb0_: if have added support to openocd to support out boards (all of xilinx should work afaict) well. with a much simpler bscan_spi proxy bitstream. if we package something it should not be xc3sprog/fpgaprog if at all possible
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<GitHub10>
[artiq] jordens pushed 1 new commit to master: http://git.io/vqYHP
<GitHub10>
artiq/master 380f498 Robert Jordens: Merge branch 'namespace_all'...
<GitHub6>
[artiq] jordens deleted namespace_all at 2674ed1: http://git.io/vqYHX
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<travis-ci>
m-labs/artiq#282 (master - 380f498 : Robert Jordens): The build has errored.
<sb0_>
mithro, this is a urjtag problem, not a migen problem
<mithro>
sb0_: the other option is to force users of migen+urjtag set up a .jtag/rc file?
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<GitHub62>
[misoc] enjoy-digital pushed 2 new commits to master: http://git.io/vqO9o
<GitHub62>
misoc/master 23541b5 Florent Kermarrec: software/bios: call eth_mode only if we have an ethernet mac (we don't need to call it when we have a hardware UDP/IP stack)
<GitHub62>
misoc/master c1ca928 Florent Kermarrec: liteeth: small logic optimizations on mac (eases timings on spartan6)
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<mithro>
sb0: Do you have any thoughts around a generic self describing debug bus for misoc - IE A low cost way for different cores to expose things like counters / states / etc and description of those elements? (Does misoc already have something like that?)
<mithro>
What does CSR stand for? Control/Status Register ?
<_florent_>
yes (unless sb0 has another meaning for it)
<mithro>
I was wonder how expensive it might be if you added CSR registers for things which wouldn't normally be directly connected to the bus?
<mithro>
what is Compiler-RT used in misoc for?
<_florent_>
it depends how many registers you want to add. But otherwise from where do you want to access to the information generated by the cores?
<mithro>
_florent_: I would want to access it from a CPU - but I wasn't sure if a large parallel bus would be more expensive than a serial bus in terms of interconnect overhead?
<mithro>
oh - it looks like someone has already invented CSR-2 bus?
<_florent_>
yes that's what we are using (CSR was 32bits IIRC)
<sb0>
ysionneau, can't the pxi6733 driver take a multidimensional array instead of the concatenation of the channel data?
<ysionneau>
as long as the driver transforms the multidimensional array into an unidimensional one I guess yes it's doable
<ysionneau>
I guess you're right that would be a better API
<ysionneau>
more high level at least
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<sb0>
why does CreateAOVoltageChan expect min/max values?
<sb0>
and is the unit volts?
<sb0>
for the samples
<ysionneau>
yes unit is Volt
<ysionneau>
I don't know exactly why you need to specify the min/max value :/
<sb0>
will there be a bug?
<ysionneau>
if the min / max value is wrong?
<ysionneau>
I honestly don't know
<ysionneau>
the documentation doesn't say much about what the min/max are for
<ysionneau>
" The minimum value, in units, that you expect to generate."
* ysionneau
is googling a bit more
<ysionneau>
I see some forum threads saying the min/max is useful for Analog *input* to select one of different input range to best fit the expected input values
<ysionneau>
but for output ... maybe there are several output stages for different voltage ranges, dunno
<sb0>
why does the daqmx also need to know about the sample rate?
<sb0>
is it setting up some aliasing filter?
<sb0>
will bad things happen if the clock is stopped?
<ysionneau>
what is sure (because we tested) is that if the clock frequency does not match the sample rate, weird stuff can happen
<ysionneau>
for instance the device stopping before the end of the sample list
<ysionneau>
at first I hard coded a 1 KHz sample rate, and Katie was feeding in a 100 kHz clock, and the device stopped after a few samples
<ysionneau>
providing the correct sample rate fixed that
<sb0>
and what happens if you pause the clock?
<ysionneau>
I don't think Katie tested that
<sb0>
well, that's what some people recommended me to do ...
<sb0>
hpefully that will work
<GitHub32>
[artiq] sbourdeauducq pushed 4 new commits to master: http://git.io/vqsmz
<GitHub32>
artiq/master 2eeaa3b Sebastien Bourdeauducq: pxi6733: clean up docstring
<GitHub32>
artiq/master 2bc8286 Sebastien Bourdeauducq: pdq2/mediator: fix arm
<ysionneau>
the API description says
<ysionneau>
The sampling rate in samples per second per channel. If you use an external source for the Sample Clock, set this value to the maximum expected rate of that clock.