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<
awygle >
Do any of the SoC projects (e.g. LiteX) have conventions for discoverable peripherals?
22:22
<
awygle >
Compare PCIe (discoverable) with AXI (not discoverable, at least not by itself)
22:26
<
tnt >
No that I know. SoC usually rely on a device tree that describes them. And on a fpga especially, discoverability costs logic gates ...
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<
zyp >
shouldn't be prohibitive
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<
zyp >
if you know the address space for the peripheral bus and the alignment for each peripheral block, all you need to do is put a magic word at a given offset in each peripheral block (e.g. first register in the block)
23:18
<
zyp >
on the other hand, you might as well have a device tree or other metadata blob stored next to the bitstream in flash and just read that
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