<azonenberg>
The problem comes when i want to assign to it
<azonenberg>
I want to be able to do foo #(.NAMES{"foo", "bar"})
<azonenberg>
without explicitly padding out to NAME_BITS for each entry
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<azonenberg>
if it's packed, i think you'll get weird results
<azonenberg>
the unpacked syntax works when used in a one module, but as soon as i use it in a different module (copy pasted exact same syntax) i get compilation failures that suggest parser errors
<azonenberg>
i.e. complaining a port i have doesn't exist
<azonenberg>
oh, innnteresting
<azonenberg>
so it looks like it works as long as i always override the parameter
<azonenberg>
i can't not specify a value
<daveshah>
That's always needed for params isn't it, at least in classic Verilog?
<azonenberg>
this is SV. And even in classic V you can have default values for parameters
<azonenberg>
But it looks like for whatever reason, that doesn't work in this code
<daveshah>
Oh, I thought you meant you weren't giving it a default value
<daveshah>
misread, sorry
<daveshah>
Suspect this is a Vivado bug
<azonenberg>
What? those never happen
* azonenberg
hides
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<azonenberg>
Achievement unlocked: got a "not implemented" error in vivado
<azonenberg>
Lol
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<tnt>
Can someone explain how the 'ALIGNWD' works on the IDDRX2F ?
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<whitequark>
azonenberg: have you looked at how strings actually work in verilog?
<whitequark>
no direct relation to your issue, just a curiosity
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<Finde>
ugh verilog strings
<Finde>
we have testbenches which take filenames to open as plusargs and they don't work across simulators
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<azonenberg>
whitequark: They're not fun
<azonenberg>
Finde: i found a vivado bug, still unfixed afaik, in which strings with embedded nul characters are handled wrong
<whitequark>
azonenberg: i see you have indeed looked.
<whitequark>
i found a yosys bug a while ago
<whitequark>
where it assumed "" is a 0-width signal
<azonenberg>
whitequark: oh it's worse than that
<azonenberg>
vivado borks horribly if you have "foo\0bar"
<whitequark>
yeah
<azonenberg>
the LRM permits this
<whitequark>
actually hang on, it's still not fixed it looks?
<azonenberg>
The forum post was ignored essentially, nobody said they were going to do anything about it
<azonenberg>
I havent tested recently
<azonenberg>
my post "incorrect synthesis of strings containing 0x00 bytes in vivado 201.2 (also tested in 2016.x"
<azonenberg>
ise 14.7 is the only tool i found that worked
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<azonenberg>
yosys failed in a different way, although i think it's since been fixed?
<azonenberg>
if you look up the forum post, i replied to the guy's misunderstanding (confusing "" and "
<azonenberg>
(confusing "" and "\0")
<azonenberg>
and then the thread died - in 2017
<azonenberg>
afaik no action was ever taken
<whitequark>
azonenberg: the problem with yosys was that it'd emit "" in write_verilog if it needed a 0-width value
<whitequark>
whereas the only thing LRM permits for that is {0{1'b0}}
<whitequark>
which is kind of bizarre frankly
<whitequark>
if they banned them completely, that'd be very inconvenient but understandable
<azonenberg>
yeah my problem was that "foo\0" was synthesized as {8'hx, "foo"}
<azonenberg>
or was it 8'hz? dont remember, either way
<azonenberg>
the nul completely disappeared and the string got shifted
<whitequark>
yeah
<whitequark>
i suspect yosys has more bugs still, i should scour its codebase for those someday
<azonenberg>
I've been out of the yosys game since $sidegig got me into systemverilog
<azonenberg>
i now write 100% SV which is incompatible with yosys
<whitequark>
there are a few (!) SV frontends now that can be glued onto yosys
<whitequark>
two i think
<azonenberg>
Although at some point i need to try synthing some of my current code with yosys and see exactly which features it chokes on
<azonenberg>
verific is the only one i know of, which is either $$$$$ or noncommercial license afaik
<whitequark>
no, i mean two FOSS SV frontends
<azonenberg>
oh?
<whitequark>
give me a sec to find them
<mwk>
daveshah: so I just got badly burned by a hold time violation on spartan 6
<mwk>
as it turns out, the OSERDES2 is one of the few primitives with significant non-negative hold time
<mwk>
1.27ns to be exact
<mwk>
(according to the data sheet, though ise timing analyzer shows something different *sigh*)
<mwk>
and nextpnr connects the relevant input to a FF output (cko 0.405 ns) via 0.332 ns routing
<mwk>
so.... assuming I can somehow magically instantly obtain all relevant timing data, does nextpnr know how to deal with the problem (ie. insert extra delay)?
<mwk>
or am I just completely screwed?
<daveshah>
Nope, you'd need a pass to deal with this
<daveshah>
There isn't even hold time analysis in master yet, although I can prioritise that now there is an actual use case for it
<daveshah>
For now particularly without all the data the best hack is probably something that adds a couple of route through LUT1s on OSERDES inputs...
<mwk>
ohhh
<mwk>
yeah, LUT1s, that would work
<mwk>
good idea, thanks
<daveshah>
Heck, a crude hold timing fix up pass could even be done in Yosys for now
<daveshah>
add LUT1s until the LUT depth at an input >= N
<mwk>
(I mean, I also have *setup* time violations I need to take care of, but I'm hoping for general packing improvements to help with those)
<daveshah>
Well, setup violations are easy, just reduce the clock :)
<mwk>
there's a little problem
<mwk>
the memory on the board I'm dealing with has a minimum clock requirement of 125MHz according to the data sheet
<daveshah>
Is it DDR of some kind? Usually they work much lower than the minimum clock particularly if the DLL is disabled
<mwk>
and the CPU is pegged to memory clock at 1:2
<daveshah>
This has been my experience with litedram anyway
<mwk>
hmm.
<mwk>
it did not for me
<daveshah>
Interesting
<mwk>
but then, I didn't know about the hold violation stuff back then
<mwk>
so perhaps it's nto the clock frequency that was the problem
<daveshah>
Have you actually tested with the vendor tools? That would rule out the memory
<mwk>
oh
<mwk>
wait, I did
<mwk>
or uhh
<mwk>
okay, I tested with 20MHz I think
<mwk>
I could try doing 75MHz
<mwk>
that should fix the setup time problems at least
<daveshah>
might be worth that
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