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<kc8apf>
xc7a50t PCIe block supports up to 4 lanes. Is it possible to use them as 2 separate x2 ports?
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<ZombieChicken>
Altera Cyclone IV EP4CE40F23 <- has that chip been reverse engineered?
<mwk>
no
<ZombieChicken>
ty
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<OmniMancer>
daveshah: so it seems the tools show a pip like this: x16y41_e6mid6.x16y42_n2mid6, but when I check what bits this produces it's the same as connecting it to n2beg6 so I am unsure what this is about :/
<daveshah>
Very odd
<daveshah>
Might just be a wire naming oddity?
<OmniMancer>
makes me wonder if there is something weird about the 2 length wires or what
<OmniMancer>
it might just have those names mapped to the beginning of the wire regardless?
<OmniMancer>
most curious
<OmniMancer>
daveshah: there are also some settings that seem to be resilient to fuzzing, but that might be because there are interdependencies :/
<hackerfoo>
Now I just need to add necessary signals that are missing, if any.
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<azonenberg>
rqou: did you see that github issue re xc2par?
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<ZirconiumX>
ZipCPU: Read your sdspi spec, even if not the actual RTL. It does seem like a very nice interface to use, and I might use it as a reference.
<ZipCPU>
ZirconiumX: Let me invite you to do so
<ZipCPU>
... if I haven't already
<ZirconiumX>
My signal names are probably going to be different to yours, but it'll be interesting to compare approaches
<ZipCPU>
I will need to modify the interface subtly when I create the SDIO version, but I do want to keep the spec's nearly identical
<ZipCPU>
If I make any changes, it would be to make the "hidden" register more visible
<ZirconiumX>
Something which comes to mind is that your spec should probably have a base address parameter of some kind for wishbone
<ZipCPU>
Not at all. That's handled by the interconnect. The core never needs to know its base address.
<ZipCPU>
The core only gets two address lines--so the interconnect can place its base address anywhere with the upper bits
<ZirconiumX>
Given I'm using a *bus* topology, I have no interconnect, unless nmigen-soc tries to handle it internally.
<whitequark>
nmigen-soc has a Decoder, which according to Wishbone terminology is "interconnect"
<ZirconiumX>
Right, okay
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<ZirconiumX>
ZipCPU: What happens if you try to read from an empty FIFO in SDSPI?
<ZirconiumX>
I can't find mention of it in the spec