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<_whitenotifier-3> [whitequark/libfx2] whitequark pushed 1 commit to master [+1/-0/±0] https://git.io/fj6op
<_whitenotifier-3> [whitequark/libfx2] whitequark 5879db8 - Add a novel interrupt-safe queue implementation.
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<azonenberg_work> mithro: re your question the other day about custom risc-v instructions with two output registers
<azonenberg_work> i wouldnt even be worried about the encoding
<azonenberg_work> adding a second register file write port is the big deal
<azonenberg_work> because that will ~double the area of your regfile
<azonenberg_work> and do wonders for timing as well
<tnt> or be multicycle ...
<azonenberg_work> Yeah that too, but that will mess with the pipeline a bunch
<azonenberg_work> by having an instruction that doesn't retire in one cycle
<azonenberg_work> normally you have stalls earlier on if you e.g. block on ram
<azonenberg_work> but writes commit one per cycle any time an instruction finishes executing
<azonenberg_work> so adding a second writeback stage complicates things a lot
<cr1901_modern> I'm guessing a custom insn will be relatively rare, so it might be okay to eat the stall
<cr1901_modern> Well, I would anyway :P
<azonenberg_work> yeah i'm thinking about the impact on verification etc too
<emeb> Yet Another RISC V FPGA Project (YARFP) -> https://github.com/emeb/up5k_riscv
<emeb> Only thing (possibly) unique is that it uses two instances of the UP5K hard SPI IP cores.
<cr1901_modern> there's always room for more softcores
<azonenberg_work> i still want to try making a tiny super optimized rv32 core, possibly using clifford's picorv32 RTL as a base
<azonenberg_work> but with hand tuned placement as a "hard macro"
<azonenberg_work> see if i can outperform the P&R tool
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<sorear> that’s why N,N+1 is so common - you do odd-even banking instead of dual port
<sorear> even better if it’s an aligned register pair
<sorear> (all of this assumes non-renamed, but if you’re doing renaming you’re probably not asking for advice here)
<Hoernchen> reminds me of adapteva's epiphany, which can do a 64bit load into even+odd 32bit regs
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<whitequark> sorear: OH THAT'S WHY
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