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<danderson>
verilog noob question: should I expect synthesis to FPGA to preserve initializations of registers, as in `reg [31:0] ctr = 32'hFFFFFFFF;` ?
<danderson>
empirically the answer is no, but I'm reading in some places that initialization should be respected when synthesizing to FPGA (but not to ASIC processes)
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<danderson>
never mind, figured it out. Now I'm learning about debouncing my inputs :P
<danderson>
(had a button input to zero the register. Turns out it's briefly active coming out of reset, so my register was getting zero'd on boot)
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<danderson>
On the plus side I got to implement my first synchronizers and debouncers, so that's neat.