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<stevekolb>
merry christmas y'all (:
<thardin>
veri logmas
<stevekolb>
Not sure if this is a yosys or rather a nextpnr topic but I am currently tinkering with my first gateware design and am looking for ways to understand what parts of my rtl code are responsible for which portions of logic/device utilization and max frequency / "max delay posedge".
<stevekolb>
Is there something sort of like a profiler that I can use to understand how I filled up my fpga, and how I broke the timing budgets?
<pepijndevos>
ERROR: Unexpected character in JSON file: '-'
<pepijndevos>
I think the IOB don't actually have a pad port maybe, so the top level port may just be dangling.
<stevekolb>
So I have started poking the json output of yosys a bit, counting cells occupied by modules/wires/registers. Rough stats show some unproportionate cell allocations for stuff I expected to be trivial (like 10k cells for one 32bit output reg?)...
<stevekolb>
Not sure how meaningful my data science here is tho, given that I don't really understand the semantics of that json data yet...
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<jfcaron>
Is there a good book other learning resource for learning to use the ice40? I got an icoBoard, but these scattered blog posts and youtube videos are not getting me very far. I can cargo-cult the LED blink demos but I think I need more thorough materials.
<jfcaron>
book or other*
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