clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<cr1901_modern> Before I spend hours reading the source: how is the implementation of the equiv_induct command different from running yosys-smtbmc in induction mode and delegating to an external SMT solver?
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<daveshah> My understanding is that it does some name based matching of registers to help the proof
<cr1901_modern> yosys doesn't have a built in SMT solver (?) but it does have minisat; is equiv_induct using minisat to run the proof instead?
<daveshah> Yes
<daveshah> No SMT involved
<mwk> equiv_induct does not do register matching; the wrapper equiv_opt pass does
<mwk> equiv_induct requires you to already have preexisting $equiv cells
<cr1901_modern> equiv_opt was the pass I was looking at, but I wanted to see how equiv_induct works first
<cr1901_modern> Anyways, nothing wrong with using SAT of course, other than "I won't be able to follow how the pass works without SMT niceties" :P
<daveshah> I think you could use something like equiv_miter with write_smt2 if you wanted
<daveshah> But its not a route I've personally tried
<cr1901_modern> hmmm
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<cr1901_modern> So, afaict "miter -equiv" annotates two modules with the same ports with XOR gates on the outputs, and equiv_miter does something analogous with existing $equiv cells in the design?