clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<gtw> I have a question about the behaviour of MemoryDffWorker::handle_rd_cell()...
<gtw> The calls to find_sig_before_dff( sig_data, ..., true ) fail to match if the output bits are a strict subset of the memory bits. For instance, if there are any read ports reading only 7 bits of an 8-bit wide block RAM.
<gtw> This small example: https://gist.github.com/garytwong/650f48f7b222623317f324a14925abde maps to block RAM as written, but if you change the "7" on line 5 to 6 or smaller (ignoring the MSB), then the MEMORY_DFF pass does nothing (saying "no (compatible) $dff found".
<tpb> Title: Trivial block RAM module · GitHub (at gist.github.com)
<mwk> I think there's an open issue for that already
<gtw> Oh :)
<gtw> Thanks, I'll try searching...
<tpb> Title: memory_dff does not merge registers into read ports with unused bits · Issue #1854 · YosysHQ/yosys · GitHub (at github.com)
<gtw> Haha perfect... I should have looked first!
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