<bwidawsk>
ZipCPU› hmm, maybe the other pins are grounded
<ZipCPU>
If you look at page 39, it shows a 16 pin flash, of which only 6 are used
<ZipCPU>
Some are grounded, some are test points
<bwidawsk>
yeah, okay, I hadn't dug that deeply
<ZipCPU>
I've written about how to build a QSPI flash controller that's highly configurable, yet very low logic
<ZipCPU>
The basic approach works nicely for dual SPI as well (strapped MISO+MOSI together for bidirectional data lines)
<ZipCPU>
While I have a regular SPI flash controller, it's not quite so configurable
<bwidawsk>
so... I was under the impression that I can program this flash with jtag, and then on subsequent boot, the bitstream would be loaded into the fpga?
<ZipCPU>
Yeah, that's usually how this sort of thing works. I usually load my design via JTAG, and the program the flash through the design, but I'm probably just strange that way
<ZipCPU>
*then program
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<bwidawsk>
well, if you know what you're doing, that's probably much faster
<bwidawsk>
I'm not sure if I need any straps, or something set to make it load from the SPI, but nothing seems to work for me
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<bwidawsk>
for whatever it's worth, I spent 3 days struggling with diamond and flexlm to get the blinky to work, and symbiflow/trellis worked within 30 seconds
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<ZipCPU>
straps? "I'm not sure if I need any straps" I'm not sure what you are referring to there
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<bwidawsk>
ZipCPU› sorry, I was half awake. Was referring to any shunts, or switches on the board
<ZipCPU>
;) By the time you wrote it, I was already snoring
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