00:11 <naobsd> at office now... let's read log

00:11 <naobsd> btw I will be busy this week and I have to restore git repos at first :(

00:22 <naobsd> oops, wrong channel

12:10 <selfbg> Can someone help me generate update.img for nand flash? I have working image on sd-card and want to transfer it?

13:08 <datmw> Astralix: I actually read the backlogs :-)

13:15 <datmw> Thanks for your advice. can you tell me the reason? In my product i employ a high quality switching PSU with both overvoltage and short protection. In previous projects I used the same psu to supply a rpi via gpio without problems. what are the hurdles with RR pro?

16:18 <AstralixNB> datmw: The rock has simple 1N4148 protection diodes at the DEBUG UART input. If you connect a 5V signal, you try to drive the VCC_IO plane of the board to 5V-0.7V=4.3V

16:19 <AstralixNB> This will either kill your TX driver as the rock might draw extreme power or some parts on the rock will get level shifted and latch up. In that case the rock is dead.

16:21 <AstralixNB> The RX/TX lines are not protected by Schottky / Zener diodes that ensure that your USB stick will loose the battle in that case. So please only use 3V3 USB dongles.

16:22 <AstralixNB> You might reuse your 5V dongle if you add a resistor divider... however, it may result in not reading anything too as the thresholds are different for 5V logic compared to 3V3 logic.

17:18 <datmw> Astralix: Sry, just tell me when I'm getting annoying with my questions, I'm just a computer science guy trying to get familiar with electronics ;-)

17:21 <datmw> I just took my multimeter and measured VCC and VDD on my board and both show me straight 5V when measured against GND pins. So how could level shifting occur when I supply power over those pins? Just to avoid miscommunication: I'm talking about J8/40 and J12/39

17:25 <datmw> have to correct myself: nothing on vdd (j8/40)

20:27 <Astralix> datmw, if I follow the schematics of rock1, I can only see that VDD_IO must be 3.3V. If you look at the not populated 4th pin of the rock (on the preview boards there are only 3 pins for the debug port) there is written 3.3V.

20:27 <Astralix> Sou you should not apply more than 3.3V

20:28 <Astralix> Taking the schematics fore reference, you can see that on the debug port are simple 1N4148 standard diodes that have a forward voltage of 0.7V.

20:28 <Astralix> So if you supply 5V over the RX/TX pins, you can substract 0.7V and have 4.3V left.

20:29 <Astralix> On the other end of this VDD_IO there is a switching regulator chip. This chip will now try to regulate your 4.3V down to 3.3V

20:30 <Astralix> So one of the components from your USB-dongle supply, USB dongle drivers, USB serial converter, rock protection diodes, rock DC/DC converter will loose the battle.

20:33 <Astralix> As you supply a pin of the SOC with a voltage higher than it's own reference supply, it may happen that the internal protection diodes of this port melt through and short your 5V to the VDD_IO reference layer of the SOC. In that case the SOC will die by the so called latch up effect.