04:56 <promach> DocScrutinizer05: do you have any idea why 16550 UART needs to have two separate 8-bits divisor latches instead of one single 16-bit divisor latch ?

13:55 <DocScrutinizer05> promach: for stuff like 1200/75 or somesuch? generally for different baud speeds for TX and RX

13:56 <promach> what 1200/75 ?

14:22 <DocScrutinizer05> 1200bd uplink, 75bd downlink

14:23 <DocScrutinizer05> or vice versa

15:00 <promach> DocScrutinizer05: have you ever used 1.5 stop bits for UART ?

15:00 <DocScrutinizer05> nope :-)

15:01 <DocScrutinizer05> actually stopbit settings are non-critical

15:03 <DocScrutinizer05> it's the least severe "error" that can happen in serial transmission. sending with one stopbit and receiving with 2 is "worst", causing an error flag but no data corruption or other problems. Sending with two or 1.5 and receiving with 1 stopbit goes unnoticed

15:05 <DocScrutinizer05> after all when you have a delay in providing next byte to send, you have an arbitrary high number of virtual stopbits anyway

15:08 <DocScrutinizer05> basically you need the stopbits only to have an edge to sense when next startbit arrives at RX

15:09 <DocScrutinizer05> so in theory you could even use zero stopbits, which would rely on delays and bytes ending with a stopbit-level bit, to sync the RX hardware to TX

15:11 <wpwrak> 0 stop is likely to get you a lot of framing errors, even if you always have a little bit of delay. also, implementations probably won't look for a start bit until after the stop bit time (after all, they're still checking for framing errors at that point)

15:12 <DocScrutinizer05> I said "in theory". There are no RL implementations of that

15:12 <DocScrutinizer05> afaik

15:13 <DocScrutinizer05> any implementation would of course *not* check for framing errors

15:15 <wpwrak> ok. joerg's UART+. well, why not. i guess it would work. you'd just have to make sure you get _any_ edge every once in a while, for clock synchronization.

15:16 <DocScrutinizer05> there are encodings (some sort of modified NRZ?) that don't use "stopbits" and introduce an escape of sorts (a special 'inverted' symbol) when too many bytes in a row don't provide an implicit "stopbit" symbol, I.E last bit sent is not different to the startbit-symbol for too long

15:16 <wpwrak> or "bit stuffing"

15:16 <DocScrutinizer05> this is not called UART though

15:18 <wpwrak> .. which may be what you mean with the inverted symbol

15:18 <DocScrutinizer05> yep

15:19 <DocScrutinizer05> I was a tad fuzzy with that description above. It's literally over a decade since I last looked into it

15:19 <wpwrak> i.e., tx: if you've sent N zero bits and are about to send another zero, send a one first, and reset the counter

15:19 <DocScrutinizer05> :nod:

15:19 <wpwrak> rx: if you've received N zero bits, discard the next one. if the next is a zero, raise hell.

15:19 <DocScrutinizer05> :nod: 2

15:20 <DocScrutinizer05> the "escape"