<Astro-_>
right now I'm fighting with zc706 qspi transfers leaking into each other, though I stop the peripheral in between.
<Astro-_>
flash chip timing for SPI CS is at 5ns which is way faster than my println!() call...
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<mtrbot-ml>
[mattermost] <sb10q> @hartytp @weidazhang does WRPLL still work if we put the transceiver PLL into the loop? i.e. use TXOUTCLK as "main DCXO input" for the DDMTD core
<mtrbot-ml>
[mattermost] <sb10q> the advantage of doing this is the stupid xilinx divider non-determinism is dealt with without additional components. the disadvantage is I don't know if the loop is still low-noise or even stable
<mtrbot-ml>
[mattermost] <sb10q> otherwise we have to take the auxiliary output of IBUFDS_GTE as "main DCXO input", and then add something that compares IBUFDS_GTE vs. TXOUTCLK and uses the TXPI to fix the divider issue
<mtrbot-ml>
[mattermost] <sb10q> (that's for the "no external FFs" case, on kasli2 and sayma rtm)
<mtrbot-ml>
[mattermost] <sb10q> the TXPI is rather annoying in multi-channel mode
<mtrbot-ml>
[mattermost] <sb10q> well, on the other hand the TXPI solution has the additional advantages that 1. we can use it to tune S/H timing in the DRTIO RXSynchronizer 2. it is required for the external FF solution anyway
<mtrbot-ml>
[mattermost] <sb10q> and 3. the GTP PLL craps out, sometimes irreversibly until FPGA is reconfigured it would seem, when enabled and not clocked properly - which would make wrpll experimentation tedious
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<mtrbot-ml>
[mattermost] <sb10q> well the si549 helper clock (at least as received by FPGAs) is flimsy, both on amc and rtm ...
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<ZirconiumX>
So, I downloaded Quartus Pro (Cyclone 10GX support is free)
<ZirconiumX>
They changed
<ZirconiumX>
*everything*
<ZirconiumX>
quartus_map? Gone, use quartus_syn instead
<ZirconiumX>
altiobuf_*? Gone, use gpio instead
<ZirconiumX>
altddio_*? Gone, use gpio instead
<ZirconiumX>
Even better, the naming of ports of gpio is not compatible with that of altiobuf/altddio
* ZirconiumX
cries
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