<ZirconiumX>
Iterating over Pins does not yield a list of Signals like I thought it would. I should go back to sleep.
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<ZirconiumX>
Okay, I'm genuinely not sure how to request a connector because platform.request works on resources, and connectors are not resources
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<cr1901_modern>
I would like to my nmigen examples, but I haven't updated them for 0.1 yet, and... at some point I needed to take a step back for the sake of my own bandwidth
<cr1901_modern>
would link to*
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<adamgreig>
is it possible to bodge nmigen into giving me a read port with a different width to the write port? just setting rport.data=Signal(n) seemingly did not do it
<adamgreig>
(this is on ice40, so in theory the hardware does support it)
<daveshah>
I think the problem is that Yosys (and RTLIL) doesn't support such a thing
<whitequark>
ZirconiumX: you can't request a connector
<whitequark>
you have to define a resource using that connector
<ZirconiumX>
Okay
<ZirconiumX>
Another question. A project I've been contracted for requires a DDR2 controller, so I planned to use litedram, which is oMigen. If I want to use that from nMigen, is it easiest to turn it to Verilog and then use it as an Instance?
<whitequark>
that's one option yes
<ZirconiumX>
Okay, thank you
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<whitequark>
uhm
<whitequark>
ZirconiumX: good news: I discovered that one weird trick can full_pipeline.py synthesize more than 5 times faster
<whitequark>
about 5.5 times.
<whitequark>
the bad news is that i can't ship the weird trick
<whitequark>
I guess you can try using this https://paste.debian.net/1116406/ if you only synthesize that code, not simulate it with e.g. iverilog
<ZirconiumX>
whitequark: I mean, ostensibly another cheat method is to completely bypass the nMigen hierarchy by synthesising each file to a module and then using Instances.
<whitequark>
sure. you could even automate it with connect_rpc.
<ZirconiumX>
In other news, I have a Versa board now
<whitequark>
nice
<ZirconiumX>
Complete with the "5G" on the board scribbled through in permanent marker
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<whitequark>
uh
<whitequark>
but nothing is passing an option -q here?..
<ZirconiumX>
Oh I see what's going wrong here.
<ZirconiumX>
It's my dumb adapter script
<ZirconiumX>
So pebcak
<ZirconiumX>
Yay, I got it fixed
<_whitenotifier-f>
[nmigen] whitequark commented on pull request #268: class Memory: allow to set default `simulate` value for all generated memory blocks. - https://git.io/Jeosd
<_whitenotifier-f>
[m-labs/nmigen] whitequark pushed 2 commits to master [+1/-0/±3] https://git.io/JeoGJ
<_whitenotifier-f>
[m-labs/nmigen] whitequark fe400b5 - test: add tests for build.plat.Platform.add_file.
<_whitenotifier-f>
[nmigen] whitequark commented on pull request #269: Platform.add_file(): Allow to add same file with same content multiple times. - https://git.io/JeoGU
<_whitenotifier-f>
[nmigen] whitequark closed pull request #269: Platform.add_file(): Allow to add same file with same content multiple times. - https://git.io/JewD4