sb0 changed the topic of #m-labs to: https://m-labs.hk :: Mattermost https://chat.m-labs.hk :: Logs http://irclog.whitequark.org/m-labs
_whitelogger has joined #m-labs
mauz555 has joined #m-labs
mauz555 has quit [Ping timeout: 252 seconds]
futarisIRCcloud has joined #m-labs
_whitelogger has joined #m-labs
mauz555 has joined #m-labs
mauz555 has quit [Remote host closed the connection]
mauz555_ has joined #m-labs
mauz555_ has quit [Remote host closed the connection]
balrog has quit [Quit: Bye]
balrog has joined #m-labs
mauz555 has joined #m-labs
mauz555 has quit [Ping timeout: 258 seconds]
sb0 has joined #m-labs
_whitelogger has joined #m-labs
<_whitenotifier-9> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±2] https://git.io/fjOdU
<_whitenotifier-9> [m-labs/nmigen] whitequark ce1eff5 - hdl.rec: implement Record.connect.
<_whitenotifier-9> [nmigen] whitequark closed issue #31: Record.connect is missing - https://git.io/fh6hw
rohitksingh has joined #m-labs
<_whitenotifier-9> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fjOdI
<_whitenotifier-9> [m-labs/nmigen] whitequark 083016d - back.rtlil: only expand legalized values in Array/Part context on RHS.
<_whitenotifier-9> [nmigen] whitequark closed issue #51: strange error with arrays - https://git.io/fjU2o
<_whitenotifier-9> [nmigen] whitequark commented on issue #51: strange error with arrays - https://git.io/fjOdL
<whitequark> migen apparently creates clock domains that are used anywhere in the design if they are not explicitly instantiated
<whitequark> is this actually desirable? to me it feels like it could read to non-obvious bugs
<whitequark> e.g. forgetting to rename AsyncFIFO's domains would leave them hanging
<_whitenotifier-9> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/522657557?utm_source=github_status&utm_medium=notification
<_whitenotifier-9> [nmigen] Success. 85.8% (+0.12%) compared to f22106e - https://codecov.io/gh/m-labs/nmigen/commit/ce1eff5464e57cb92b073aa1cc86aaa75bb4f423
<_whitenotifier-9> [nmigen] Success. 100% of diff hit (target 85.67%) - https://codecov.io/gh/m-labs/nmigen/commit/ce1eff5464e57cb92b073aa1cc86aaa75bb4f423
<_whitenotifier-9> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/522658253?utm_source=github_status&utm_medium=notification
<_whitenotifier-9> [nmigen] Success. 85.8% (+0%) compared to ce1eff5 - https://codecov.io/gh/m-labs/nmigen/commit/083016d747f25b67a6e06fab9d29fa46b4fe4d1b
<_whitenotifier-9> [nmigen] Success. 100% of diff hit (target 85.8%) - https://codecov.io/gh/m-labs/nmigen/commit/083016d747f25b67a6e06fab9d29fa46b4fe4d1b
rohitksingh has quit [Ping timeout: 246 seconds]
<_whitenotifier-9> [m-labs/nmigen] whitequark pushed 2 commits to master [+0/-0/±3] https://git.io/fjOd8
<_whitenotifier-9> [m-labs/nmigen] whitequark 33f9bd2 - hdl.ast: accept Signals with identical min/max bounds.
<_whitenotifier-9> [m-labs/nmigen] whitequark 360bc9b - hdl.ast: improve tests for exceptional conditions.
<_whitenotifier-9> [nmigen] whitequark closed issue #58: fix Signal(max=1) - https://git.io/fjYx6
<_whitenotifier-9> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/522664583?utm_source=github_status&utm_medium=notification
<_whitenotifier-9> [nmigen] Success. 85.81% (+<.01%) compared to 083016d - https://codecov.io/gh/m-labs/nmigen/commit/360bc9b5b462db641af92f4670f81819f3e26dcc
<_whitenotifier-9> [nmigen] Success. Coverage not affected when comparing 083016d...360bc9b - https://codecov.io/gh/m-labs/nmigen/commit/360bc9b5b462db641af92f4670f81819f3e26dcc
<_whitenotifier-9> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fjOdH
<_whitenotifier-9> [m-labs/nmigen] whitequark 85ae99c - back.rtlil: emit `nmigen.hierarchy` attribute.
<_whitenotifier-9> [nmigen] whitequark closed issue #54: Hirarchy of submodules is not obvious from verilog - https://git.io/fjkXd
<_whitenotifier-9> [nmigen] whitequark commented on issue #54: Hirarchy of submodules is not obvious from verilog - https://git.io/fjOdQ
<_whitenotifier-9> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/522669373?utm_source=github_status&utm_medium=notification
<_whitenotifier-9> [nmigen] Success. 85.82% (+0.01%) compared to 360bc9b - https://codecov.io/gh/m-labs/nmigen/commit/85ae99c1b47931d51422ed9ac6bf24bec5fb7fc9
<_whitenotifier-9> [nmigen] Success. 100% of diff hit (target 85.81%) - https://codecov.io/gh/m-labs/nmigen/commit/85ae99c1b47931d51422ed9ac6bf24bec5fb7fc9
<_whitenotifier-9> [nmigen] whitequark commented on issue #3: Ensure that all submodules are added to the design - https://git.io/fjOdN
mauz555 has joined #m-labs
mauz555 has quit [Ping timeout: 240 seconds]
mauz555 has joined #m-labs
<_whitenotifier-9> [m-labs/nmigen] whitequark pushed 2 commits to master [+0/-1/±22] https://git.io/fjOFT
<_whitenotifier-9> [m-labs/nmigen] whitequark 44711b7 - hdl.ir: detect elaboratables that are created but not used.
<_whitenotifier-9> [m-labs/nmigen] whitequark aed2062 - Remove examples/tbuf.py.
<_whitenotifier-9> [nmigen] whitequark closed issue #3: Ensure that all submodules are added to the design - https://git.io/fpbth
<_whitenotifier-9> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/522678277?utm_source=github_status&utm_medium=notification
<_whitenotifier-9> [nmigen] Failure. 85.76% (-0.07%) compared to 85ae99c - https://codecov.io/gh/m-labs/nmigen/commit/aed2062101afe14336cfca36cc22cb6f585c3795
<_whitenotifier-9> [nmigen] Success. Coverage not affected when comparing 85ae99c...aed2062 - https://codecov.io/gh/m-labs/nmigen/commit/aed2062101afe14336cfca36cc22cb6f585c3795
mauz555 has quit [Ping timeout: 258 seconds]
mauz555 has joined #m-labs
mauz555 has quit []
rohitksingh has joined #m-labs
sb0 has quit [Quit: Leaving]
_whitelogger has joined #m-labs
cr1901_modern has quit [Ping timeout: 246 seconds]
cr1901_modern has joined #m-labs
cr1901_modern1 has joined #m-labs
cr1901_modern has quit [Ping timeout: 246 seconds]
mauz555 has joined #m-labs
mauz555 has quit []
<mtrbot-ml> [mattermost] <sb10q> whitequark: that's done to make migen produce a useful output by default - export clock and reset signals as inputs
<mtrbot-ml> [mattermost] <sb10q> otherwise they would be undriven by default
<whitequark> sb: why not a hard error?
<mtrbot-ml> [mattermost] <sb10q> so you can demonstrate migen with fewer lines of code. not terribly important though, having a hard error is also acceptable
<whitequark> ok
<mtrbot-ml> [mattermost] <sb10q> iirc that behavior is disabled if the user creates any clock domains
<whitequark> oh I see, I misunderstood how that worked
<mtrbot-ml> [mattermost] <sb10q> so, in most real-world designs, that won't cause issues with things like forgetting to add ClockDomainsRenamer on a FIFO
<mtrbot-ml> [mattermost] <sb10q> also, Vivado errors out if you have I/O pins that are not constrained
<mtrbot-ml> [mattermost] <sb10q> so even with the default behavior, that would be automatically caught eventually
<whitequark> that varies by toolchain
<whitequark> so you can't rely on it
<whitequark> i think it is OK if the platform always creates some clock domain
rohitksingh has quit [Ping timeout: 246 seconds]
X-Scale has quit [Ping timeout: 246 seconds]
cr1901_modern1 has quit [Quit: Leaving.]
cr1901_modern has joined #m-labs
<cr1901_modern> whitequark: https://gist.github.com/cr1901/5de5b276fca539b66fe7f4493a5bfe7d I created a gist of all the clock domain behavior semantics a few months ago. Dunno how relevant it is, but here: https://gist.github.com/cr1901/5de5b276fca539b66fe7f4493a5bfe7d
<cr1901_modern> err, double link
X-Scale has joined #m-labs
rohitksingh has joined #m-labs
<mtrbot-ml> [mattermost] <sb10q> is sci-hub down?
<mtrbot-ml> [mattermost] <sb10q> trying to get http://sci-hub.tw/10.1364/AO.19.001223 but it doesn't work
<cr1901_modern> Website exists, but I can't download it either
<whitequark> cr1901_modern: thanks, this helps
rohitksingh has quit [Ping timeout: 244 seconds]
rohitksingh has joined #m-labs
_florent_ has left #m-labs [#m-labs]
rohitksingh has quit [Ping timeout: 246 seconds]
ZirconiumX has quit [Ping timeout: 258 seconds]
<lkcl> hmmm, it *might* be the case that the removal of unnecessary elaboratables is being overaggressive
<lkcl> m.submodules += Array() where the Array is a suite of modules results in important signals being destroyed
<lkcl> whereas m.submodules.child1 = Array()[1]
<lkcl> m.submodules.child2 = Array()[2]
<lkcl> etc.
<lkcl> works fine
<lkcl> this since a git pull from about... 36 hours ago
<lkcl> self.rs = Array(rs)
<lkcl> m.submodules += self.rs
<lkcl> used to work fine
<mtrbot-ml> [mattermost] <astro> artiq windows-no-hardware-tests work on hydra now
<mtrbot-ml> [mattermost] <astro> but extended-tests (kc705) hang on test_rtio_log