#m-labs on 2019-03-15 — irc logs at freenode.irclog.whitequark.org

2018-12-09 21:21 sb0_ changed the topic of #m-labs to: https://m-labs.hk :: Logs http://irclog.whitequark.org/m-labs

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06:20 <attie> cr1901_modern: It's my PhD thesis project, using FPGAs to do graph processing.

06:21 <attie> It's typical academic code, not really meant to be usable by other people. For instance there's a severe lack of output, all it reports is how long it took to execute the algorithm, because that's what goes into the paper :)

06:29 <cr1901_modern> attie: There's also no documentation :P

06:30 <cr1901_modern> also typical ;)

06:30 <cr1901_modern> well no readme*

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09:44 <bb-m-labs> build #2486 of artiq-board is complete: Failure [failed anaconda_upload] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2486 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>

09:44 <bb-m-labs> build #2965 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2965 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>

10:28 <bb-m-labs> build #2487 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2487

10:30 <bb-m-labs> build #2966 of artiq is complete: Failure [failed python_unittest_2] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2966 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>

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15:31 <sb0> rjo: do you think this may cause the 55ns sayma sync bug? https://github.com/m-labs/artiq/blob/master/artiq/examples/kasli_sawgmaster/repository/sines_urukul_sayma.py#L33-L38

15:31 <sb0> i.e. inside sawg

15:45 <rjo> sb0: how? if the ftws are different the relative phase would drift, not be at a constant offset. the ftw lsb is 0.25 Hz. you'd see that.

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16:20 <sb0> rjo: yes sure, but what about the initialization? can there be something wrong with the initial sawg phase?

16:23 <rjo> sb0: how are you setting the absolute phase?

16:37 <rjo> sb0: explain this: https://github.com/m-labs/artiq/blob/master/artiq/examples/kasli_sawgmaster/repository/sines_urukul_sayma.py#L72

16:38 <rjo> sb0: with the 64 bit compiler issues in mind i would try a simpler approach.

16:40 <rjo> sb0: take a frequency that is comensurate with the rtio frequency. use absolute phase mode in sawg. align the time cursor some multiple of the period. clear the phase. set the frequency.

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16:41 <rjo> why is it 17 and not 16?

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