00:11 <mithro> What is the correct way to make a register which is reversed or another register?

00:23 <cr1901_modern> mithro: For loop assigning each bit position in the source reg to the reverse of the dest register. In principle, Cat() should support iterating backwards, but no synthesizer will accept the output Verilog.

00:56 <lkcl> could always use a python for-loop to manually construct a list l and then use Cat(*l)

01:22 <lkcl> using len could even make it generic

01:23 <lkcl> l = []

01:23 <lkcl> for i in range(len(srcreg)):

01:24 <lkcl> l.append(srcreg[len(srcreg)-i])

01:25 <lkcl> destreg = Signal.like(srcreg)

01:25 <lkcl> destreg.eq(Cat(*l))

01:25 <lkcl> mithro: that should do the trick, in a generic way

01:32 <lkcl> can you tell i really don't like python list INcomprehension? :)

04:40 <cr1901_modern> sb0: https://github.com/m-labs/migen/pull/164 Should be ready, I addressed everything you asked for.

09:51 <kbeckmann> could you do srcreg[::-1] or will that just become some strange garbage?

09:57 <GitHub-m-labs> [migen] whitequark pushed 1 new commit to master: https://github.com/m-labs/migen/commit/3fc11b5a1dc1e66fa5997dd2124908ae34e3e1e3

09:57 <GitHub-m-labs> migen/master 3fc11b5 Adam Greig: build/lattice/icestorm: update package list for iCE40-HX8K.

09:59 <bb-m-labs> build #344 of migen is complete: Failure [failed python_unittest] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/344 blamelist: Adam Greig <adam@adamgreig.com>

22:54 <mithro> whitequark: Do you have an example of a test which read/writes to csr registers / wishbone bus / SRAM memory?

22:54 <whitequark> mithro: context?

22:55 <mithro> whitequark: Simulation tests in migen

22:55 <whitequark> errr, let me show you the API

22:57 <mithro> whitequark: Basically, I want to test writing to the CSR registers and having the thing respond as I expect...

22:57 <whitequark> yeah, gimme a sec

23:01 <mithro> whitequark: Would also be good if you had any example of filling sram with data

23:01 <mithro> ahh ha -> https://github.com/m-labs/migen/blob/dcfec40c9d0cd3abab264897b424f0f53eeb58b4/examples/sim/memory.py

23:02 <whitequark> mithro: yeah

23:02 <whitequark> so for CSRs

23:02 <whitequark> you can just do `yield from some.mod.csr.read()`

23:02 <whitequark> and `yield from some.mod.csr.write(x)`

23:03 <whitequark> you can look at their implementations in misoc/interconnect/csr.py

23:10 <mithro> whitequark: Do you have an example of multiple clock domains with simulation at all?

23:43 <whitequark> not offhand

23:44 <lkcl> so i'm looking at the verilog.py generator and it doesn't look like there's a way to generate "parameters"

23:45 <whitequark> like localparam?

23:45 <lkcl> yes

23:45 <lkcl> output reg `fetch_output_state output_state

23:45 <lkcl> );

23:45 <lkcl> parameter mtvec = 32'hXXXXXXXX;

23:45 <lkcl> parameter reset_vector = 32'hXXXXXXXX;

23:45 <lkcl> however Instance you *can* pass *in* parameters

23:45 <whitequark> yeah

23:46 <whitequark> that's accurate

23:46 <lkcl> would simply passing in the "parameters" as input variables do the trick, do you think?

23:46 <lkcl> or, should i cheat and pass them in as python class __init__ parameters? :)

23:50 <lkcl> i'm going to just treat them as module inputs, see how i get on, as i want to make use of Instance rather than have one huge verilog file