sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<GitHub141> [ionpak] sbourdeauducq pushed 5 new commits to master: https://github.com/m-labs/ionpak/compare/5431780700a7...8abeff05a11c
<GitHub141> ionpak/master 4da2836 Sebastien Bourdeauducq: get ADC samples as ints
<GitHub141> ionpak/master 63c6544 Sebastien Bourdeauducq: fix gitignore
<GitHub141> ionpak/master 3393d9e Sebastien Bourdeauducq: add Ethernet TVS and error latch errata
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<rjo> hartyp: yes. you also did excellent work on the spec. we should try formalize/streamline/accelerate the review process for the other/next projects.
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<GitHub30> [ionpak] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/ionpak/commit/a39c95e2768e39442b144ff7e13b21eea6b6d520
<GitHub30> ionpak/master a39c95e Sebastien Bourdeauducq: HV PID control (untested)
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<hartytp> rjo: thanks. Agreed though, while we're getting to a good result in the end, the current specification/review process is a bit ad hoc and inefficient
<hartytp> Can you remind me:
<hartytp> 1. Is ARTIQ support for the FMC on Sayma already funded (e.g. to use with the FMC to VHDCI + VHDCI carrier)?
<sb0> what kind of "support" would that be?
<hartytp> 2. What is the status of Kasli ARTIQ support? DRTIO slave only? Or, is using it as the master also funded?
<hartytp> e.g. can I run a Zotino off Sayma?
<hartytp> We discussed how this would work before, but I wasn't clear if it was actually funded yet
<sb0> well, just "running a Zotino off Sayma" is basically adding the pins and core and recompiling the gateware (in theory at least, assuming vivado doesn't crash etc.)
<sb0> for schemes that would not require gateware recompilation there are three ways:
<sb0> 1) find a set of peripherals in a single gateware config that would satisfy everyone
<sb0> 2) do some soft-muxing of the FPGA pins e.g. between SPI and TTL
<sb0> 3) do gateware partial reconfiguration with something like recobus
<sb0> #1 might not really require funding, #2 may be funded via opticlock (rjo?), #3 is complicated, requires fpga reverse engineering, and is not funded
<sb0> hartytp, by the way, have you seen ionpak? you commented about this project a few months ago
<hartytp> sb0, right. I though we agreed on option (2). See #164
<hartytp> sb0. Yes, I'd had a look over it. Looks nice.
<hartytp> Out of interest, are you interested in building that as an end in itself, or do you have a particular application in mind?
<sb0> I've been experimenting with vacuum systems for a while, trying to build a small ion trap, and found many things particularly frustrating
<sb0> so I'm fixing that a bit
<sb0> after the ionpak there will be a QMS controller and then a laser servo, also single-board, with modern parts, and relatively easy to build
<sb0> servo all integrated with fpga, adc/dac, HV generator and piezo driver, peltier driver for temp regulation, etc.
<whitequark> I'm in a rather similar position; off-the-shelf hardware is either ridiculously expensive or in an unknown state when purchased used
<whitequark> and the latter tends to be outdated and quite hard to assemble in a manageable system
<whitequark> I've been meaning to design something quite like ionpak for a while but sb0 beat me to it
<sb0> yes, or even when purchased new it is outdated, e.g. the SRS100 uses a 80186 CPU
<sb0> whitequark, you should visit shenzhen
<GitHub99> [ionpak] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/ionpak/commit/0cb8d0c53d5f4b381b93c0beee45a6233b1fe40c
<GitHub99> ionpak/master 0cb8d0c Sebastien Bourdeauducq: pid: use Option instead of NaN
<whitequark> sb0: any particular reason?
<sb0> lots of electronics and people who can design or manufacture it efficiently
<GitHub128> [ionpak] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/ionpak/commit/15c9bafb512ab7f707bd03af2e5c5c34e53d47b0
<GitHub128> ionpak/master 15c9baf Sebastien Bourdeauducq: reset error latch at startup
<hartytp> sb0 -- cool. What do you want to trap?
<hartytp> are you planning to design all of that hardware yourself?
<hartytp> We're planning (when someone has time) to build a simple pelter driver using one of these https://www.thorlabs.com/drawings/57160dceea1e3737-AC819F2D-5056-2306-D95DA23810B7D908/MTD415L-DataSheet.pdf + a micro for ethernet
<sb0> is there something that I don't know about peltier drivers?
<sb0> I'd just do that with a H bridge + thermistor + MCU, but I've seen all sorts of complicated designs
<sb0> or just a mosfet instead of the H bridge if you only want to cool
<hartytp> That's about all the Thorlabs chip is. Just depends how much one wants to do oneself versus buying it in a convenient package. In our case, while the electronics is fun, we're pretty short on time
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<sb0> if you're already adding a MCU for ethernet, you might as well just add mosfets instead of this proprietary thorlabs thing
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<sb0> hartytp, oh and probably calcium, since the laser diodes are relatively easy to procure
<sb0> hartytp, for ethernet on the mcu, maybe you can just reuse the ionpak code
<hartytp> sb0: from #148 I get the impression that the default bitstream for Sayma AMC will have the FMC configured for muxed TTL/SPI phys, and so should be fine for Zotino
<hartytp> re temp controller: I did think about that. If I have time, I would be interested in having a play with that. We'll see though if/when I find the time...
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<GitHub176> [ionpak] whitequark pushed 1 new commit to master: https://github.com/m-labs/ionpak/commit/d6bfba821e69fde6f7b42c308001107f427beb40
<GitHub176> ionpak/master d6bfba8 whitequark: Unbreak ADC interrupt.
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<GitHub121> [ionpak] whitequark pushed 1 new commit to master: https://github.com/m-labs/ionpak/commit/8353ffbe983f57522c40f0a20a137bb5a8e0d829
<GitHub121> ionpak/master 8353ffb whitequark: Update errata.
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