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<stekern>
nice! ;)
<ysionneau>
stekern: I wonder if there is some dedundance between orpsoc tool and migen framework
<ysionneau>
in the way it generates a soc and the interconnects
<stekern>
there definitely is, I was suggesting in the wake of it that we should consider migen for it. But at that point migen wasn't very mature, and development took another turn
<ysionneau>
and now Olof put a lot of effort into orpsoc ... so it's delicate
<stekern>
fusesoc, he's as fond of namechanges as this project ;)
<ysionneau>
I remember I talked to him about migen back in Cambridge but I never took the time to do a demo to him :/
<ysionneau>
ah yes fusesoc :)
<stekern>
we're using bits and pieces from the milkymist project in it anyways
<stekern>
the verilog minimac is there, and stuff from the uart
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<ysionneau>
it just seems now that migen stuff is very powerful for building SoCs
<stekern>
I agree
<FabM>
++
<ysionneau>
++
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<sb0>
stekern, did you get the boot to work?
<sb0>
in milkymist-ng-mor1kx
<sb0>
here it freezes after the BIOS tries to pass control to the loaded program
<stekern>
IIRC, yes.
<stekern>
it was a while ago though...
<sb0>
did you use a different crt0 for the software payloads? I'm using the same as for the BIOS
<sb0>
maybe it doesn't call the right exception handler
<stekern>
but I remember that I did comparisons between coremark for lm32 and mor1kx on the board, so I guess I did get that running at least
<sb0>
hmm, crt0 loads SPR_EVBAR... so that sounds right
<sb0>
stekern, isn't the 4th function parameter stored in r6, not r7?
<stekern>
right... did you found a bug? ;)
<sb0>
it still doesn't work when I use l.jr r6 though
<sb0>
ah, now it does
<stekern>
maybe I never did try it like that... but just loaded software straight into flash or something
<sb0>
it's just that my payload had a large bss and took a while to start
<sb0>
memtest works, 10Gbps bandwidth
<sb0>
I guess that the highest amount of bandwidth openrisc has ever controlled :-P
<stekern>
;)
<stekern>
yeah, I use that sucky xilinx mig thing on my atlys board, I should investigate using your controller instead
<stekern>
I did write a SDRAM controller myself too, but never have had time to investigate the DDRx stuff...
<sb0>
what's the fpga and memory type on atlys?
<stekern>
it's the same fpga as on m1, and DDR2
<sb0>
ah, it should be supported by the current PHY
<sb0>
we already have a (non public) board with S6 + DDR2
<stekern>
cool, I just need to get my thumb out my **** and try that out then =)
<stekern>
I could probably reuse some of your hdmi stuff as well, I've been beyond lazy and just used a hacked up version of the xilinx whitepaper for that
<stekern>
...and do you know the ironic part is, that's the only piece of code I've experienced brokage in when switching between ISE versions...
<sb0>
urgh, that xilinx code is horrible
<stekern>
I'm not going to argue with you on that...
<sb0>
I cannot count how many bugs and kludgy components I've found in that
<sb0>
so, openrisc-controlled hdmi video mixing seems to work, too
<ysionneau>
funny the l. prefix on instructions, I guess it's to say it's an instruction playing with "long" words
<stekern>
you probably want a l.nop after that l.jr r6, to fill the delay slot
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<stekern>
and yes, I will gladly take the blame for it missing in the first place ;)
<stekern>
I will however not take the blame for the r6 vs r7 bug, the boot_helper was called like this back when I did that code: boot_helper(r1, r2, r3, r4, addr);
<sb0>
I thought you removed that delay slot?
<ysionneau>
IIRC there is a version of or1k with and without delay slot
<ysionneau>
same for toolchain
<GitHub109>
[misoc] sbourdeauducq pushed 2 new commits to master: http://git.io/WlnoFw