lekernel changed the topic of #m-labs to: Mixxeo, Migen, MiSoC & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<rjo> lekernel: oh my.
<rjo> lekernel: i think the 2) that you implemented is probably good enough. especially since the representation of integers is not preserved anyway. everything becomes a decimal number. and the fact that they are now also always positive is not so much of an additional issue.
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<GitHub186> [misoc] sbourdeauducq pushed 1 new commit to master: http://git.io/t9AS2g
<GitHub186> misoc/master 9aa474c Sebastien Bourdeauducq: gitmodules: use https and m-labs
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<GitHub29> [migen] sbourdeauducq pushed 3 new commits to master: http://git.io/aPosUw
<GitHub29> migen/master adffec3 Sebastien Bourdeauducq: utils/misc: add gcd_multiple function to compute GCD or any number of integers
<GitHub29> migen/master adda930 Sebastien Bourdeauducq: fhdl/simplify: add FullMemoryWE decorator that splits memories to remove partial WEs
<GitHub29> migen/master c13fe1b Sebastien Bourdeauducq: specials/Memory: allow for more flexibility in memory port signals
<GitHub32> [misoc] sbourdeauducq pushed 1 new commit to master: http://git.io/EuMZvQ
<GitHub32> misoc/master 860f273 Sebastien Bourdeauducq: make: add decorator option
<lekernel> hmm, yosys seems to hate initialized memories
<larsc_> I think there was a post saying that he recently added support for this
<lekernel> I removed them; now I get this
<lekernel> 26.9.5.1. Executing ABC.
<lekernel> ABC: ABC command line: "read_verilog /tmp/yosys-abc-IuvjWB/input.v; read_lut /tmp/yosys-abc-IuvjWB/lutdefs.txt; strash; balance; dch; if; write_blif /tmp/yosys-abc-IuvjWB/output.blif".
<lekernel> ABC: Warning: Performing LUT mapping with 4022 choices.
<lekernel> ABC:
<lekernel> ERROR: Syntax error in line 115!
<lekernel> line 115 of input.v is just
<lekernel> wire n113; // $add$/home/sb/M-Labs/misoc/verilog/lm32/submodule/rtl/lm32_cpu.v:1573$1511.alu.V[24].adder.t2
<lekernel> there are many similar ones before that don't seem to cause problems
<lekernel> but I'm perhaps looking at the wrong file
<larsc_> yep, that was the thing I was talking about
<larsc_> the max line length for blif files is 4096
<lekernel> ah, did you investigate?
<larsc_> in his parser
<lekernel> probably worth emailing him, he fixed the lm32 problems in a couple days
<lekernel> well, except that one perhaps
<larsc_> I actually started rewriting the parser
<larsc_> to be token based rather than line based
<larsc_> but writing parsers in C is always so annoying
<lekernel> larsc_, do you have any workaround?
<larsc_> increase the buffer size in passes/abc/blifparse.cc
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<lekernel> wow, it produced a misoc netlist
<lekernel> but then
<lekernel> ERROR:NgdBuild:196 - On or above line 906729 in file "simplesoc-mixxeo.edif":
<lekernel> Problem parsing "rename". This likely means that the EDIF netlist was
<lekernel> improperly written. Please contact the vendor of the program that produced
<lekernel> this EDIF.
<larsc_> 'line 906729'
<larsc_> that's a big file
<lekernel> yeh :)
<lekernel> it took a lot of time to produce, too
<lekernel> I think it's unreasonable to expect it would work
<lekernel> 87MB
<larsc_> the cache probably takes up quite a bit of space considering the is no bram or dram support
<lekernel> "ASIC-like clocking" - did they finally manage to make FPGAs that are not slow?
<davidc__> lekernel: at the moment? merely warm vapour exhaled by marketing people.
<davidc__> Apparently 'Kintex Ultrascale' is their new stupid name for '8'-series parts
<lekernel> yeah, it smells a lot of that
<davidc__> (given that the whole 7 lineup isn't shipping yet, I figure its still 3 years off)
<larsc_> yea, I think it's just marketing bs
<davidc__> by asic-like-clocking, they probably mean "actually working clock gating" or something else
<larsc_> yes
<larsc_> so you can save power
<davidc__> er, wait "not-explicitely-marked-as-broken-but-still-broken-anyways clock gating"
<davidc__> Just like dynamic reconfig in S3 + S6 series...
<lekernel> it says "ASIC-like clocking for scalability, performance and lower dynamic power" :)
<lekernel> well, maybe they mean the performance of a 1995 ASIC or something
<larsc_> they probably don't mean anything by it, it just sounds good ;)
<davidc__> lekernel: if you want ASIC-like performance in an FPGA, I'll sell you one! (while the FPGA achieves ASIC-like performance + power consumption, the builtin 1-ton FIB used for reconfiguration uses slightly more. It also takes 6 months to reconfigure the design)
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<GitHub16> [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/OThtHg
<GitHub16> migen/master 3196462 Sebastien Bourdeauducq: add support for Verilog include paths
<GitHub106> [misoc] sbourdeauducq pushed 2 new commits to master: http://git.io/hUN8wA
<GitHub106> misoc/master c95b9d6 Sebastien Bourdeauducq: gensoc: use add_verilog_include_path
<GitHub106> misoc/master ba46cd3 Sebastien Bourdeauducq: make.py: update description
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<GitHub106> [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/CAdaTw
<GitHub106> migen/master a20688f Sebastien Bourdeauducq: fhdl/simplify/FullMemoryWE: fix WE slice for multi-port mems
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