<ndufresne>
I added that in gst after wondering for a whise why a simple clock overlay would cause corruption when using UVC to Intel DRM data transfer (DRM side allocating)
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<ndufresne>
jernej, thanks for the links, it's quite interesting how this code calls DrmFD a DMABuf
<ndufresne>
but in the context of a DRM renderer it make sense
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<pgreco>
wens, updating xorg-x11-server to 1.20.4 fixed the crash, thanks!
<pgreco>
montjoie, 5.0.10 booted normally
<pgreco>
5.1rc6 is still crashing at boot (still without your patches)
<pgreco>
but I'm not seeing again what I think I saw about crypto, so forget it for now :)
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<suprothunderbolt>
anyone know if the user manual for the A64 is wrong on the I2S register locations or this sun4i-i2s.c code is wrong? It's using the sun4i locations for things where as the sun8i defines are the same as the offsets in the user manual.
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<anarsoul>
suprothunderbolt: did you notice the name of quirks struct?
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<suprothunderbolt>
sun50i_a64_codec_i2s_quirks?
<anarsoul>
yeah
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<anarsoul>
suprothunderbolt: *codec*
<suprothunderbolt>
ahh
<suprothunderbolt>
sdo it's actually using one of the other quirks sections?
<suprothunderbolt>
h3?
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<anarsoul>
suprothunderbolt: other 3 i2s are compatible with h3
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<suprothunderbolt>
thanks. I was thinking of just removing all the support for other chips so it didn't confuse me but might not need to ;)
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<codekipper>
suprothunderbolt: why don't you post logs, your changes and maybe scope images. Stripping things out on something that works isn't going to help.
<suprothunderbolt>
oh it was just to help with me getting confused :) I disabled a bunch of the other I2C stuff in the DTS because I wasn't using it and it was making debugging harder. I think I'm close to getting things working now though
<codekipper>
Ideally you want the codec attempting to play something and then get a dump of the reg settings. I've used a handful of codecs with the A64 and HDMI audio which also uses the i2s.
<suprothunderbolt>
codekipper: only thing I'm confused about now is if LRCK_width should be 128 or 256
<codekipper>
although TDM isn't supported yet...it should play 2 channels
<suprothunderbolt>
yeah, now I'm onto getting TDM to work.
<codekipper>
that may depend on the amount of channels in your case...if it's just two then I think it should be 32
<suprothunderbolt>
for 8, so it needs to be either 128 or 256 I think
<suprothunderbolt>
I need 256 BCLK in a LRCKL period
<suprothunderbolt>
the docs say "PCM mode: Number of BCLKs within (Left + Right) channel widthI2S / Left-Justified / Right-Justified mode: Number of BCLKs within each individual channel width (Left or Right)"
<codekipper>
128 clocks per cycle....256 total
<suprothunderbolt>
I'm running in left justified mode, so I assume it's then 128
<suprothunderbolt>
I'm a bit confused about PCM_TXnCHSEL
<codekipper>
have you changed any of the code?...can you also post your dts changes.... 0x58 0x1234567 looks suspicous
<suprothunderbolt>
as I don't understand there being multiple TX when there aren't multiple data lines / serialisers. Either way I've just enabled one of them.
<suprothunderbolt>
it does look funny being numbered like that
<suprothunderbolt>
0x58 is the channel mapping so I think that's correct, though i think the other way would work as well
<suprothunderbolt>
i.e. 0x76543210
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<wens>
it is always possible the IP block itself has multiple data lines, but the package doesn't expose them
<suprothunderbolt>
wens: yeah, that's what I was assuming
<wens>
and the datasheet could have copy/paste errors :/
<suprothunderbolt>
i'm hoping zero is the one that's connected :)
<suprothunderbolt>
oh and I've forced the MCLK enable, BCLKDIV 2 MCLKDIV 1
<suprothunderbolt>
so MCLKDIV should be 512 fs and MCLK should be 256 fs
<suprothunderbolt>
sorry MCLK should be 512, DIV is 1.
<suprothunderbolt>
MODE_SEL I'm a bit confused about
<codekipper>
0x34 and 0x44 are the important registers here.
<codekipper>
0x58 is the Rx channel settings
<codekipper>
I'll try and dig out some logs with playback working...
<suprothunderbolt>
yeah, I'm just testing record at the moment
<suprothunderbolt>
arecord -vvv -c8 -f dat > /dev/null
<suprothunderbolt>
easy to check if that's doing anything as I've just got a signal gen going into it
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<suprothunderbolt>
the TXEN and RXEN bits are disabled at the moment but GEN is enabled
<suprothunderbolt>
so I think I should enable those
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<suprothunderbolt>
there's also a flag for SDO0_EN but not the input pin.
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<suprothunderbolt>
oh RX/TX might not be yet enabled when that logging is printed
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<suprothunderbolt>
LRCKL is coming out at 48 Khz on the scope. MCLK and BCLK look correct BCLK is 12.288 mhz
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<fALSO>
bom dia
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<codekipper>
suprothunderbolt: RXEN is enabled during capture 0x0 0x60013
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<codekipper>
I've only ever tested capture successfully using hardware loopback...setting bit 3 in I2S/PCM_CTL
<codekipper>
other people have confirmed 32bit 192KHz capture for signal analysis
<suprothunderbolt>
I'm not getting anything on any of the data pins of the codec looking at it on the scope. I've got an idea about what might be going on and I'll have another look at that tomorrow.
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