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<micken>
robmur01: thanks
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<micken>
robmur01: ok, but smc enters something in ATF (monitor?) and then exists?
<micken>
exits
<micken>
I am reading smc calling convention gguide
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<micken>
robmur01: just replacing hvc with smc , give 0x0 in r0 , so if the psci function actually runs, it would indicate success. But it doesn't jump to the entrypoint address
<micken>
robmur01: and if I enter a bogus value in arg 2 (r1) it returns -2
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<micken>
and a read of mpidr returns with only bit 31 set
<micken>
that doesnt sound right
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<micken>
robmur01: and settinbg target core to 0x0 returns already on ... so I must miss something
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<micken>
I meant , it means that CPU_ON is ok, but it doesn't jump to entry_point_address
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<robmur01>
micken: welcome to herding cats ;)
<robmur01>
don't expect anything to "jump" as such - after the SMC returns, the boot CPU will simply carry on executing - it's up to you what to do with it
<robmur01>
at the same time, the new CPU will start executing from the entrypoint in AArch64 EL2
<robmur01>
so you probably want the entrypoint to at least initialise VBAR and do some basic setup
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<micken>
robmur01: ok. thanks again. I didnt expect it to switch to aarch64 (from aarch32)
<micken>
psci code in u-boot is just a shell
<micken>
quite empty
<micken>
writing a small handler now for it
<mmind00>
micken: you might want arm-trusted-firmware instead, maybe?
<micken>
dunno yet
<mmind00>
micken: aka there is a complete process already established to build uboot+atf ... with working psci
<micken>
that handler was for the switch , not u-boot
<micken>
mmind00: ok? I am using BLOB uboot (cant get to aarch32 in mainline)
<mmind00>
ok
<robmur01>
is RiscOS itself SMP these days?
<robmur01>
because if not, then you may as well leave the boot CPU in AArch64 at EL2 to do the juggling and launch the big CPU straight at your current "drop to 32-bit EL1 and continue" routine
<robmur01>
otherwise, yes, you'll need a tiny "hypervisor" at EL2 to marshal between AArch32 EL1 and AArch64 EL3
<micken>
ok
<micken>
not much smp in riscos
<micken>
if the hypervisor needs to be aarch64, then do it in u-boot is the only option
<robmur01>
in principle I think you could build upstream ATF to enter EL2 in aarch32, but then you'd have to build a 32-bit u-boot for RK3399
<robmur01>
which would almost certainly be "fun"
<micken>
heh :D
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<micken>
sigh , time to learn arm64 asm
<maz>
pretty much the same as 32bit, tbh...
<maz>
just without conditionals....
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<pcbBob>
Hi :) Anyone here who might want to share the TRM for the RK2918?
<pcbBob>
Or give me a hint where I might be able to find it? I only found a very short TRM and the datasheet (which doesn't provide enough information)
<pcbBob>
Not much happening in the linux for rockchip world?
<vagrantc>
plenty happening
<pcbBob>
But not TRM for RK2918?
<pcbBob>
*no
<vagrantc>
many people from a wide variety of timezones in here ... patience :)
<micken>
soo
<micken>
as soon as I touch mon mode I end up in atf?
<micken>
seems like it
<micken>
cant overwrite mvbar
<micken>
cant switch to mon32 for doing it
<micken>
I am too stupid to understand the macro asm that switches to el1-aarch32 :D
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<pcbBob>
there were some people asking for RK2918 datasheet and they never got a successfull response so I guess Rockchip just doesn't want to know us about the RK2918?
<inode>
pcbBob: my guess is it's possibly a case of appeasing large customers who believe in security through obfuscation
<inode>
i've been looking for the RK3229 TRM for a while
<inode>
obfuscation/obscurity
<pcbBob>
What is so interesting about the RK2918 is that it actually supports SRAM, DDR, DDR2 and DDR3 as external memory
<pcbBob>
But what you are saying is that there is one large customer which does not want anyone else to know about this chip but this customer only bugs RK2918 (and RK3229) but not the other ones for which TRMs have been released?
<pcbBob>
*buys
<inode>
yes, but like i said it's just a guess
<inode>
i came to this conclusion after i wrote a request for the reference manual to rockchip, and once i had disclosed that i'm just an individual without any business interest in its application - i was then told to consider making use of single board computers which feature their other SoCs with publically available documentation instead
<pcbBob>
So you actually got an answer?
<pcbBob>
That's surprising to me
<inode>
yes i did
<pcbBob>
Maybe I write an e-mail about the RK2918
<pcbBob>
What was your contact? Just their webpage?
<inode>
i hope you have better luck than i did :)
<inode>
let me check my mailbox, brb
<pcbBob>
Thanks!
<inode>
i wrote to opensource@rock-chips.com initially, and i probably got this address from their website
<pcbBob>
Thanks, I will try :)
<inode>
pushing my luck here - but do you by any chance have the TRMs for MT8321 or SC7731? ;)
<pcbBob>
No I am sorry. I have access to one chinese forum and they freely share some datasheets, but that forum doesn't have any information about the two ICs you just mentioned
<inode>
thanks for checking
<pcbBob>
May I ask you why those specific CPUs? inode
<micken>
robmur01: OK: so trying many different aproches , but I need to know what catches my smc 0
<micken>
robmur01: I am not sure of where the best place is to do the cpu_on , right now I try it as first thing in the switch to aarch32
<micken>
setting up the cpu can be done in kernel
* micken
is singing sdcard blues
<micken>
Hoho
<micken>
I am returning
<micken>
I do the smc and after the smc I have a stoploop
<micken>
at the entry point defined I print a 'E' and I get that 'E'
<inode>
pcbBob: the SC7731 is fairly common in low cost smartphones, and the MT8321 seems to serve a similar role for low cost tablets
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<inode>
it would be ideal to be able to pick up an affordable mobile device right off the shelf of a local shop and then have the option to ditch the questionable software/firmware that is inevitably shipped with it
<micken>
robmur01: after the macro for switching to el1 it stops.. I assume that it should be loading from boot entry by then
<micken>
the function in transisitions.S calls the macro and do no more
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<micken>
I am in rom again!
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