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<hardik_>
Hi All, I just replaced my debian rootfs(425M size) with buildroots 2M size rootfs......but ethernet not working here ....then i enabled ethool but still it's not working
<hardik_>
so what are the drivers i need to install to make ethenet working.....i'm compiling kernel from outside (custom one)...using buildroot only for rootfs
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<stdint>
hardik_, the ethernet driver is at your kernel
<stdint>
hardik_, have you seen your ethernet device and please paste your kernel log
<stdint>
geekerlw, you don't meet problem, just keep it
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<geekerlw>
stdint, now playing may stop. you set MPP_SET_OUTPUT_BLOCK_TIMEOUT to -1, so when get_frame from mpp, it will be blocked in pthread_cond_wait
<stdint>
geekerlw, I never meet that
<stdint>
it certainly should be blocked
<geekerlw>
I remove the reset func in change_state, working well now
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<micken>
lo
<micken>
Is there any special things I need to do when writing to VOP config_done?
<micken>
I have configured VOP_BIG , but when I write "1" to config_done , I get a data abort
<ayaka>
micken, have you configure the iommu
<micken>
ayaka: ok
<micken>
oh no I haven't but u-boot probably has
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<micken>
I have configured GRF_SOC_CON6 to connect vop to hdmi
<micken>
I have reseted hdmi
<micken>
I configed vop to have hdmi output enabled
<micken>
I set the background to a color
<micken>
config_done
<micken>
acording to the very small hdmi notice in trm , it should be setup for 1080p at poweron and only needs a reset
<micken>
But the real documentation for HDMI is missing :(
<micken>
ayaka: I can't find anything that is called iommu in the docs, is it something related to iomux?
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<micken>
by peaking in existing sources I can see that I am doing it right , assuming that the notice of hdmi is configured from poweron
<ayaka>
micken, sorry, I was leaving
<micken>
anyway even if hdmi isn't the vop shouldn't crash
<ayaka>
micken, if the power supply doesn't supply HDMI phy, when vop push data into it
<ayaka>
it should crash and shutdown a cortex of the cpu
<ayaka>
a core of the cpu
<micken>
ok that might be it
<ayaka>
micken, so you still meet a problem?
<micken>
sadly the phy isn't documented
<micken>
So I need to route power to the phy
<ayaka>
micken, which soc?
<micken>
3288
<ayaka>
ok let me find it for you
<ayaka>
micken, usually the power is controller by the PMU through GRF
<ayaka>
micken, also there are pins for HDMI used as the power supplies in the chip
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<micken>
ayaka: do I understand you right,, is there a GRF register that controls this?
<ayaka>
micken, yes I am looking it
<micken>
ayaka: thanks
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<ayaka>
CRU_CLKGATE16_CON bit 9 is for the HDMI ctrl gate, low would enable the clock
<ayaka>
I think the HDMI driver has been in the kernel
<micken>
oh but I don't do Linux :)
<ayaka>
micken, I know, using the kernel driver as a reference is the most quick way
<micken>
yes
<micken>
ayaka: so the hdmi display isn't clocked from poweron , it looks like that when I read trm
<ayaka>
micken, if you have the TRM, I think the HDMI phy must be included
<micken>
ayaka: nope , just TX
<micken>
ayaka: it reference a couple of docs , but I can't find those
<ayaka>
micken, it is what you want
<micken>
ok let me take a peek at the GRF to see if I can find the power reference
<micken>
ayaka: I find one for powering up lvds phy
<micken>
ayaka: or is the clocking makes it powered?
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<micken>
so writing 0x2000000 to CLKGATE16 would enable the clock?
<micken>
assuing write enable to bit 9 and setting it to 0
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<micken>
ayaka: enabling the crash made the config_done not to crash
<micken>
err
<micken>
ayaka: enabling the clock made the config_done not to crash
<micken>
nothing on screen yet
<micken>
ayaka: ah , I am reseting the phy and not tx. How do I reset tx?
<ayaka>
micken, it is also controlled by cru
<ayaka>
micken, CRU_SOFTRST6_CON bit 0
<micken>
ayaka: vio_arbi_hsrstn_req`?
<ayaka>
micken, not that
<ayaka>
micken, that you seen is bit 3
<micken>
not in the trm
<micken>
vio_arbi_hsrstn_req is bit 0
<micken>
ayaka: if its wrong , what is the name for the right bit?
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<micken>
oh well , trying with bit 0 now
<micken>
didn't crash , but did not help
<micken>
ayaka: is the tx setup to 1080p? like in the tx trm?
<ayaka>
micken, I never read that carefully, I am not in charge of that
<ayaka>
anyway, the u-boot also has the HDMI driver
<micken>
ayaka: yes I have been looking at that
<micken>
ayaka: but it looks quite empty
<micken>
or
<micken>
it sets up the pixelclocks if I am not mistaken
<micken>
but , the u-boot I use doesn't give any signal on hdmi (don't know if it should)
<micken>
perhaps hdmi is not enabled in it
<micken>
using mainline
<ayaka>
micken, you had better check the version at rockchip-linux github
<micken>
"The default HDMI transmitter is configured to 24bit RGB 1080P resolution video with 8 channel 48K sample I2S format audio input. It is easily for customer to turn on HDMI transmitter without doing more complex operation. Just do the step, reset the HDMI TX."
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<ayaka>
micken, I forget, have you select which vop as the hdmi source
<ayaka>
vop lite or vop big?
<micken>
yes
<micken>
just built u-boot rockchip
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<micken>
ayaka: I feel stupid , but I can't find any info on which offset I should put u-boot on the sdcard. I only have a u-boot.bin now.
<micken>
ayaka: I have worked a lot with i.MX series but this is my first project with rockchip
<micken>
I see I found it
<micken>
:D
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<micken>
it doesn't give me SPL binary
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<micken>
ok
<micken>
I am using a tinker board
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<micken>
ayaka: looking in rockchip u-boot , HDMI_PHY does have a power register (In itself) , it is located at offset 0x3000, but from where?
<ayaka>
micken, I told you there are two pins at soc
<micken>
ok I will check my backlog
<micken>
ayaka: can't find it in my backlog, we have discussed the clock
<ayaka>
micken, there are two pins for the power of the hdmi as well as eDP
<micken>
ok
<micken>
I don't know if you told me of any registers, but as before u-boot does power up PHY using offset 0x3000
<micken>
CONF0
<micken>
which is the same as BASE in the headers
<micken>
Sorry for all this
<micken>
The problem is that I just can't copy paste GPL code
<micken>
m_PDDQ_SIG PHY_CONF0
<micken>
ayaka: the docs just gives me a chunk HDMI 128K , and doesn't provide information of the contents
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<micken>
ok so the phy source adress is 0x3000
<micken>
*4 + HDMI
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<micken>
ayaka: sorry to bother you with this, please tell me if I should go somewhere else..
<micken>
ayaka: but I have one more question about phy source
<micken>
ayaka: it is a B size register according to the only reference I have, so how do I use it? Is there write protection bits or anything else I should be aware of?