marcan changed the topic of #asahi-gpu to: Asahi Linux: porting Linux to Apple Silicon macs | GPU / 3D graphics stack black-box RE and development (NO binary reversing) | Keep things on topic | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Logs: https://alx.sh/l/asahi-gpu
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<DarkShadow44>
Main goal will be having a shader assembler/disassembler in C, that could be plugged into LLVM for bytecode generation
<DarkShadow44>
Still in its early stages though...
<DarkShadow44>
Most of understanding is based on dougallj
<DarkShadow44>
Does this sound like a useful undertaking to you?
<daniels>
DarkShadow44: it depends on what your end goal is - ultimately the results of the GPU reverse engineering will result in a Mesa driver which uses Mesa's NIR compiler framework rather than LLVM
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<daniels>
NIR (like SSA) is a mostly-architecture-independent SSA IR which is good for transformations and optimisations
<daniels>
each driver (and generation within the driver) though has its own custom backend IR, which is a much closer fit to assembly and disassembly
<daniels>
so the short answer is that LLVM is not useful in and of itself. the driver won't use LLVM to implement a full compiler at any point; and for code generation and analysis in development, the driver will ultimately have its own bespoke backend IR, so a (dis)assembler will ultimately be targeted closer to that
<DarkShadow44>
well, I'm trying to 1) have a disassembler that can turn bytecode into readable assembly (for debugging)
<DarkShadow44>
and 2) to make an assembler for usage with mesa/nir
<DarkShadow44>
or whatever we end up using in the end
<DarkShadow44>
main part of that will be an immediate representation in form of structs that represent the operations the GPU can do
<chrisf>
DarkShadow44: id encourage you to enhance things that exist rather than building yet another one, if you can
<DarkShadow44>
As another abstraction, to make bytecode generation via NIR easier and more flexible when the architecture changes, e.g. with the next chips
<daniels>
oh no, please don't think about future architecture generations
<daniels>
if the new architecture has trivial changes, you don't need enough adaptation to have built an abstraction layer
<daniels>
it it has substantial changes, your abstraction layer is just going to get in the way
<DarkShadow44>
hmm depends on how much it changes
<chrisf>
or at least "not another layer beyond what we will need as the backend ir"
<DarkShadow44>
So you'd turn NIR code directly into G13 bytecode?
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<daniels>
nope, via a backend IR - I would recommend reading the blog post above to get a reasonable idea of the lines between the three (NIR, backend IR, bytecode)
<chrisf>
your instructions-as-structs model isnt wildly off
<DarkShadow44>
yeah, that's my IR
<DarkShadow44>
that's why I don't understand why you dislike that approach
<chrisf>
you need something like this. just no *additional* layer
<DarkShadow44>
layer in what sense?
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<chrisf>
in the short term i guess it doesnt matter if you go in slightly odd directions as long as it turns "?" bits into things we understand
<DarkShadow44>
well, my goal would also be to get the code upstreamed eventually
<DarkShadow44>
AFAIK there's no assembler project (in C) yet
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<DarkShadow44>
Just need to flesh out the architekture, then I consider asking for integration
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<bloom>
DarkShadow44: looks like you're having fun :)
<DarkShadow44>
bloom: Now that I finally figured out how device_load/store work, definitely :)
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