<arossdotme>
got any photo of china factorys that could be used in something say like a info graphic? from a real life photo to a simple,basic - ie: 2 colour outline,silo-wet(cant spell the word i mean) - icon representation of a factory?
<arossdotme>
or pictures along the lines of portable computer product life cycle, designed/plotted (planned) obsolescence that you have came across?
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<kristianpaul>
moin
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<whitequark>
<furan>Ihttps://github.com/cseed/arachne-pnr Arachne-pnr implements the place and route step of the hardware compilation process for FPGAs. It accepts as input a technology-mapped netlist in BLIF format, as output by the Yosys [0] synthesis suite for example. It currently targets the Lattice Semiconductor iCE40LP/HX1K FPGA [1].
<kristianpaul>
oh
<kristianpaul>
wait wait, so this is another HDL ?
* kristianpaul
clicks
<kristianpaul>
is that private whitequark ?
<kristianpaul>
nm
<whitequark>
no, not a HDL
<whitequark>
this is a PAR for lattice
<kristianpaul>
but yosys uses abc i think for PAR no?
<whitequark>
abc is for ASIC
<whitequark>
there was no OSS PAR for FPGAs so far
<whitequark>
(fpgatools don't count)
<kristianpaul>
sure not fpgatools is just foorplan
<kristianpaul>
hmm i tought yosys was doing PAR for its ice40 lib..
<kristianpaul>
still too early to speak, he commits everday..