06:50 <nic30> Hello, i have problem with migen, i would like to create handshake interface and i basic examples it works but when i try something more complicated migen puts reg at component outputs. Is there way to force migen to use multiplexor output rather than output with reg ?

06:50 <nic30> from migen.fhdl.std import * from migen.fhdl.specials import SynthesisDirective from migen.fhdl import verilog from migen.genlib.cdc import * from migen.genlib.record import * from migen.sim.generic import run_simulation

06:51 <nic30> # i will copy rather line by line....

06:51 <nic30> from migen.fhdl.std import *

06:51 <nic30> from migen.fhdl.specials import SynthesisDirective

06:51 <nic30> from migen.fhdl import verilog

06:51 <nic30> from migen.genlib.cdc import *

06:51 <nic30> from migen.genlib.record import *

06:52 <nic30> from migen.sim.generic import run_simulation

06:52 <nic30> layout_axis = [

06:52 <nic30> ("data", DATA_WIDTH, DIR_M_TO_S),

06:52 <nic30> ("strb", DATA_WIDTH // 8, DIR_M_TO_S),

06:52 <nic30> ("last", 1, DIR_M_TO_S),

06:52 <nic30> ("valid", 1, DIR_M_TO_S),

06:52 <nic30> ("ready", 1, DIR_S_TO_M)

06:52 <nic30> ]

06:52 <nic30> class hs_conection:

06:52 <nic30> def __init__(self, src, dst):

06:53 <nic30> self.src = src

06:58 <nic30> sory for code fragment now it is on github https://github.com/Nic30/my-Migen-examples/blob/master/handshake.py

07:01 <nic30> my problem is that slave_valid and master_ready have reg, i need them to by just combinational. What iam doing wrong?

08:32 <GitHub161> [artiq] whitequark pushed 1 new commit to new-py2llvm: http://git.io/vtnsp

08:32 <GitHub161> artiq/new-py2llvm 7cd6011 whitequark: Add typechecking for most builtin.

09:40 <GitHub122> [misoc] sbourdeauducq pushed 1 new commit to master: http://git.io/vtnMp

09:40 <GitHub122> misoc/master a1e3fb1 Joe Britton: flterm.py: use serial_for_url

13:45 <sb0> hi cr1901_modern

13:45 <sb0> did you get my last email about your patch?

13:47 <cr1901_modern> sb0: I haven't had power for the past 3 days, so I haven't read it

13:48 <sb0> what country is that?

13:51 <cr1901_modern> Good ol' USA, New Jersey specifically

13:51 <sb0> lol

13:53 <cr1901_modern> New Jersey got hit with a storm that took out 200,000+ resident's power on Tuesday (for perspective, this is more homes without than the last hurricane to reach land). I was one of them.

13:55 <cr1901_modern> In any case, I read your email. I ran the source file through an online PEP checker, which apparently sucks, since you still had issues with it.

13:55 <sb0> ime flake8 works pretty well and isn't a pain to install

13:57 <cr1901_modern> Will fix. In the meantime, this whole experience makes me realize I take power for granted. Need to find a way to generate my own power. At least enough to power a small fridge :/

15:28 <sb0> rjo, I cannot flash any of the pipistrello boards with xc3sprog. have you used other tools successfully?

15:33 <sb0> ah, it works with fpgaprog

15:33 <sb0> xc3sprog is remarkably buggy ...

15:35 <sb0> blergh, and you cannot flash an arbitrary binary with fpgaprog without flashing the main bitstream as well

15:36 <sb0> also, they _had_ to use a different communication protocol with the proxy bitstream, of course

15:36 <sb0> why makes things simple

15:36 <sb0> *make

15:38 <sb0> next in today's lovely bugs: accessing the pipistrello sdram too fast makes my laptop drop the USB power

15:39 <sb0> (╯°□°）╯︵ ┻━┻)

16:08 <GitHub51> [artiq] whitequark pushed 2 new commits to new-py2llvm: http://git.io/vtWg2

16:08 <GitHub51> artiq/new-py2llvm 71256a7 whitequark: Assignment rhs is typed before lhs.

16:08 <GitHub51> artiq/new-py2llvm e07057c whitequark: Add range types.

16:14 <GitHub181> [artiq] whitequark pushed 1 new commit to new-py2llvm: http://git.io/vtWVR

16:14 <GitHub181> artiq/new-py2llvm ea0d11b whitequark: Allow also passing iterables to lists.

16:24 <GitHub123> [artiq] fallen pushed 1 new commit to master: http://git.io/vtW6s

16:24 <GitHub123> artiq/master c381102 Yann Sionneau: manual: fix faq item title about determining pyserial URL by serial number

16:24 <ysionneau> rjo: (artiq_flash) set -v seems very very verbose :o

16:24 <ysionneau> maybe you meant set -x

16:24 <ysionneau> ?

16:28 <ysionneau> this kind of feature seems to output way too much, I fear it can get the user lost

16:54 <travis-ci> m-labs/artiq#254 (master - c381102 : Yann Sionneau): The build passed.

16:54 <travis-ci> Build details : https://travis-ci.org/m-labs/artiq/builds/68505113

17:01 <whitequark> ha, nist finally retracted Dual_EC_DRBG

17:04 <rjo> sb0: yeah. my jtag-spi-proxy works with two tools, there are some comments in the code.

17:04 <rjo> sb0: xc3sprog and pipistrello works fine here. it is entirely possible that my jtag-spi-proxy does not re-implement all the bugs that xc3sprog relies on.

17:04 <rjo> ;)

17:05 <rjo> ysionneau: ack. i will make it set -x

17:06 <rjo> ysionneau: i was getting annoyed by the fact that if xc3sprog fails to find the bitstream/proxy/bitstream it simply exits cleanly.

17:07 <rjo> ysionneau: the verbosity is similar for -x and -v just that one has pluses.

17:09 <GitHub101> [artiq] jordens pushed 1 new commit to master: http://git.io/vtWp3

17:09 <GitHub101> artiq/master 07ceed9 Robert Jordens: artiq_flash.sh: back down on verbosity

17:19 <ysionneau> rjo: -x only prints lines which are executed

17:19 <ysionneau> -v prints everything afaik

17:19 <ysionneau> but yes -x is also very verbose :/

17:20 <ysionneau> maybe I can add an error message for the situation you reported

17:23 <rjo> ysionneau: imho fixing at least that case in xc3sprog would be nice.

17:27 <ysionneau> "in xc3sprog" ?

17:28 <ysionneau> can't I just do if [ -f ] to test for file existence in the shell script?

17:31 <ysionneau> proxy existence is already tested btw, and should print an error message in case file does not exist

18:13 <rjo> yes. but that does not solve the bug in xc3sprog that it should not exit cleanly if it fails.

18:14 <rjo> it is actually more and fragile code in artiq_flash.sh than in xc3sprog.

18:15 <ysionneau> sure, xc3sprog has many defects

18:15 <ysionneau> but it's easier for us to patch our own code, than patching an external tool

18:33 <rjo> xc3sprog seems to be accepting patches afaict. it seems cleaner to fix bugs in code than to work around them. even if the code is broken in other places.

18:39 <rjo> sb0: i would like to make experiments have "from artiq.language import *" instead of "from artiq ...". with the later it is not clear that the "*" are exclusively language elements used to write experiments and not things like worker/master/ui etc.

19:46 <sb0> rjo, does the runtime boot on your pipistrello?

19:47 <sb0> it crashes at startup here, but that could be related to the USB power issues

20:09 <rjo> boots here

20:09 <rjo> using the binaries from conda.