<montjoie>
the best way we use is "two layer with wood"
<montjoie>
the major problem in all case remain wire management
<montjoie>
bi stable relay imply more wiring/soldering and a controller
<montjoie>
I use a cambrionix U8C 110GB (near 140€)
<montjoie>
wigyori: problem with managed usb hub is that it is expensive
<montjoie>
the only problem is that kernelci/LAVA need uboot+tftp so A80/H6 cannot be tested for the moment
<montjoie>
now 50I received my pdu, I will add all my allwinner boards
<montjoie>
my primary goal was to add maximum of qemu machines
<montjoie>
the link is a bit old test
<wigyori>
montjoie: do you have the boards listed somewhere that you do tests with? i planned to do something similar for openwrt, and so i wouldn't duplicate the boards you have, just the ones i have
<MoeIcenowy>
montjoie: from H6 view, it's really internal phy ;-)
<montjoie>
sorry
<montjoie>
arg internal phy
<montjoie>
MoeIcenowy: why not in sun8i_dwmac_power_internal_phy() ?
<montjoie>
and if only a hackish way is possible, you will have some sort of "acked-by" to do it
<montjoie>
you will loose less time finding how:)
<montjoie>
MoeIcenowy: I think the best way is "ask netdev and more precisily PHY guys" on how to made this dep, people like Andrew Lunn/Florian Fainlelli will have the right answer
<MoeIcenowy>
montjoie: maybe specify a compatible may help?
<montjoie>
unless we could make a "dependency" via the DT
<MoeIcenowy>
montjoie: I also think so
<montjoie>
and so too late
<montjoie>
MoeIcenowy: my first though is to use a custom net PHY driver, but I fear the PHY is called after being detected
<MoeIcenowy>
montjoie: 0x0014 SYS_EPHY_CTL0 contains clock gate / reset for EPHY, 0x0016 SYS_EPHY_CTL1 contains IO enable for EPHY-related pins (RMII intf and LEDs
<MoeIcenowy>
montjoie: seems that some registers in AC200 are need to be poked for the EPHY to run
<montjoie>
MoeIcenowy: what do you mean by "enable sequence" ?
<montjoie>
MoeIcenowy: I want to, but I lacked time. Now I have a pdu, the h8homlet is the first board I add for a bring back in kernelci (no a83t in kernelci since the stop of bootlin lab)
<MoeIcenowy>
montjoie: do you know where should we place the PHY's enable sequence?
2019-03-24
<MoeIcenowy>
montjoie: so you hadn't brought up H8Homlet's EPHY?
<montjoie>
MoeIcenowy: h8homlet booting with 4.16, wow my last try is a bit old
<montjoie>
I just need some soldering of the uart which are too thin for my ftdi to get good connexion
<montjoie>
MoeIcenowy: I didnt use the h8 homlet yet. But I will soon
<MoeIcenowy>
montjoie: when you're dealing with H8 Homlet board, is AC200 EPHY usable at boot w/o any AC200 register changing?
2019-03-19
<montjoie>
with relay, It need some wire modification that I try to avoid
<montjoie>
I choose my PDU because the output port is an USB port, so no need to wire hack
<montjoie>
I think yes but I need to verify
<montjoie>
but my PDU do "power usage stats per port"
<montjoie>
over usb, but it exists relay over ethernet
<montjoie>
I have tried first with relays and arduino but my soldering skill is bad
<montjoie>
PowerDistributionUnit it is for powering many devices and in my case switch each port off/on remotly
<megi>
montjoie: what is PDU? some kind of relay board?
<montjoie>
ah ah ah, I will receive my PDU today! I finnaly will can power off/on all my allwinners remotly
<montjoie>
does it exists a mainline matrix for uboot like for kernel ?
<Net147_>
montjoie: anyway, I found the issue and sent a patch to mailing list
<Net147_>
montjoie: same issue with U-Boot 2019.01 and 2019.04-rc4
<montjoie>
3.4 is too too old, 2018.09 is old
2019-03-14
<willmore>
montjoie, For H6? okay, thanks.
<montjoie>
willmore: /proc/cpuinfo show aes
2019-03-12
<montjoie>
I fear she dont have it, since I have asked her for help when i tryed to do this
<montjoie>
having it will permit to add it on kernelci
<montjoie>
I am very interested by ethernet in uboot for H6
2019-03-08
<montjoie>
angelo_ts: by crypto you mean the crypto engine ?
2019-03-06
<montjoie>
anyway I will always be worried, either "the load part is so common that's a shame not to share it" or "the process part is too different split it!"
<montjoie>
I think having a common driver begins to be too dangerous
<montjoie>
and the hardware is different
<montjoie>
I have a bug in a83t that lag me the opportunity to send sun8i-ce
<montjoie>
raaah I think I need to drop a80/a83t from sun8i-ce
2019-03-05
<smaeul>
montjoie: H6 has a "debug mode", where the ARM CPUs can loop messages back to themselves. That mode isn't documented for earlier SoCs
<smaeul>
montjoie: you would have to write a server (ARISC firmware) and a client (in Linux), and you could send whatever data you want back and forth to test
<angelo_ts>
montjoie, well ok, thanks
<montjoie>
angelo_ts: slower... not, with cyrpto engine you will have crypto a bit slower byt offloaded of cpu
<angelo_ts>
montjoie, ok., i ask what is for becouse maybe we just don't use/need it
<montjoie>
yeah I said that since months
<montjoie>
angelo_ts: crypto engine wil be sent soon
<montjoie>
smaeul: does it exists some way of testing the sunxi malibox ? For adding that in my test suite
<montjoie>
willmore: I measure a synchronous dd on a LUKS2 block
<willmore>
montjoie, what are you measuring with?
<montjoie>
yeak better with ce
<montjoie>
module
<montjoie>
perhaps its due to missing arm-ce
<montjoie>
willmore: I need to understand why the cpu way is slower than h5
<willmore>
montjoie, congrats, I think that beats what a Cortex-M3 can do at normal clocks....
<montjoie>
wow xts(ecb(aes-arm64)) is only 3.7MB/s
<montjoie>
it will be my next target when finished to mainline sun8i-ce and amlogic crypto
<montjoie>
H6 has a dedicated MMC controller with crypto EMCE
<montjoie>
my heart rebooted
<montjoie>
5.8MB/s now
<montjoie>
pfff, the image was generated on mmc and not on shm...
<montjoie>
I dreamed "4k will add too many speed ah aha h"
<montjoie>
I already use 4k block
<montjoie>
I will check with stock clock speed instead of using datasheet
<montjoie>
appart adding XTS since H6 support it, I am out of idea for the moment
<montjoie>
I set max clock of datasheet
<montjoie>
wow LUKSbench on H6 with cryptoengine 300kB/s such speed
2019-01-28
<montjoie>
not bad
<montjoie>
my first try will be with gentoo-cpuburn-emerge-gcc
<montjoie>
sorry, mislead with memoryburn
<montjoie>
java ? or firefox ?
<montjoie>
KotCzarny: one coworker just said "use cpuburn" to test
<montjoie>
I can convince to try it just for feed an allwinner performance troll
<montjoie>
willmore: I have stuff for that @work, but less time to setup it
<montjoie>
mru: I will test the offload soon
<montjoie>
I need now to try to understand why on my R40 xts(sun8i-ce-ecb) exists and not on H5
<montjoie>
willmore: yes CBC AES 256
<montjoie>
willmore: yes
<montjoie>
so a little /2 speed, finally not so serious
<montjoie>
and without sun8i-ce the speed goes to 6.6MB/s
<montjoie>
and bus-ce is driven by pll-periph0/ahb1
<montjoie>
willmore: ce is driven by pll-periph0
<willmore>
montjoie, the clock that drives the crypto unit, does it drive anything else? A clock that drives multiple things (like the AMBA or peripherial bus) is often called a 'clock domain'.
<mru>
montjoie: places like switzerland
<montjoie>
willmore: what is a clock domain ?
<montjoie>
unsigned int for the world!
<montjoie>
I always use K degree
<montjoie>
so with correct clock, it is now 3.4MB/s
<willmore>
montjoie, lol
<montjoie>
dont be so negative
<willmore>
montjoie, that's -ETOOMANYFRENCHPEOPLE
<montjoie>
ETOOMANYFRENCHPEOPLE
<montjoie>
ElBarto: I note that
<montjoie>
MegaOctet
<ElBarto>
montjoie: you know, octets isn't much used outside of France :)
<KotCzarny>
montjoie: could it be you are still missing something that bsp does?
<montjoie>
but with correct clock speed, it increase a bit
<montjoie>
willmore: mo/s
<montjoie>
and with luks2, its worse
<montjoie>
does it really offload cpu
<montjoie>
now I need to check the "offload" part
<montjoie>
wow redoing benchmark of sun8i-ce, dd on a luks image in RAM, without it 5.7mo/s with it.....1.2
2019-01-25
<montjoie>
zoobab: did you see it in the web interface ?
<montjoie>
zoobab: no
2019-01-17
<montjoie>
but it came only after some time
<montjoie>
plaes: r40
<montjoie>
do you guys, enable DMA-API DEBUG ? if yes do you get random "cpu touching an active dma mapped cacheline" ?
<montjoie>
I have encountered a NULL ptr on sound card, but it seems fixed today