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2015-05-27 01:41 <arossdotme> got any photo of china factorys that could be used in something say like a info graphic? from a real life photo to a simple,basic - ie: 2 colour outline,silo-wet(cant spell the word i mean) -  icon representation of a factory?
2015-05-27 01:44 <arossdotme> or pictures  along the lines of portable computer product life cycle, designed/plotted (planned) obsolescence that you have came across?
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2015-05-27 14:48 <kristianpaul> moin
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2015-05-27 19:04 <whitequark> <furan>Ihttps://github.com/cseed/arachne-pnr Arachne-pnr implements the place and route step of the hardware compilation process for FPGAs. It accepts as input a technology-mapped netlist in BLIF format, as output by the Yosys [0] synthesis suite for example. It currently targets the Lattice Semiconductor iCE40LP/HX1K FPGA [1].
2015-05-27 19:05 <kristianpaul> oh
2015-05-27 19:05 <kristianpaul> wait wait, so this is another HDL ?
2015-05-27 19:06 * kristianpaul clicks
2015-05-27 19:06 <kristianpaul> is that private whitequark ?
2015-05-27 19:06 <kristianpaul> nm
2015-05-27 19:07 <whitequark> no, not a HDL
2015-05-27 19:07 <whitequark> this is a PAR for lattice
2015-05-27 19:07 <kristianpaul> but yosys uses abc i think for PAR no?
2015-05-27 19:08 <whitequark> abc is for ASIC
2015-05-27 19:08 <whitequark> there was no OSS PAR for FPGAs so far
2015-05-27 19:08 <whitequark> (fpgatools don't count)
2015-05-27 19:09 <kristianpaul> sure not fpgatools is just foorplan
2015-05-27 19:11 <kristianpaul> hmm i tought yosys was doing PAR for its ice40 lib..
2015-05-27 19:11 <kristianpaul> still too early to speak, he commits everday..
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2015-05-27 19:34 <whitequark> well, it already works to a degree
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