2013-12-11 12:34 _whitelogger has joined #m-labs 2013-12-11 12:34 http://irclog.whitequark.org/m-labs 2013-12-11 12:34 thx 2013-12-11 12:34 lekernel changed the topic of #m-labs to: Mixxeo, Migen, MiSoC & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs 2013-12-11 12:34 whitequark has left #m-labs [#m-labs] 2013-12-11 13:43 jaeckel has joined #m-labs 2013-12-11 13:43 jaeckel has quit [Changing host] 2013-12-11 13:43 jaeckel has joined #m-labs 2013-12-11 13:46 Mistah_Darcy has joined #m-labs 2013-12-11 13:59 mrueg has joined #m-labs 2013-12-11 14:21 kristianpaul has joined #m-labs 2013-12-11 14:21 kristianpaul has joined #m-labs 2013-12-11 14:27 kristianpaul has quit [Ping timeout: 264 seconds] 2013-12-11 14:33 kristianpaul has joined #m-labs 2013-12-11 14:33 kristianpaul has joined #m-labs 2013-12-11 15:26 antgreen has joined #m-labs 2013-12-11 15:41 xiangfu has quit [Remote host closed the connection] 2013-12-11 15:44 antgreen has quit [Ping timeout: 245 seconds] 2013-12-11 16:05 Mistah_Darcy_ has joined #m-labs 2013-12-11 16:06 davidc__ has joined #m-labs 2013-12-11 16:06 Mistah_Darcy has quit [Ping timeout: 246 seconds] 2013-12-11 17:33 Mistah_Darcy_ has quit [Ping timeout: 265 seconds] 2013-12-11 17:40 sh4rm4 has joined #m-labs 2013-12-11 18:03 Mistah_Darcy has joined #m-labs 2013-12-11 18:34 rjo has joined #m-labs 2013-12-11 18:46 jevin has joined #m-labs 2013-12-11 18:54 jevin has quit [Quit: Textual IRC Client: www.textualapp.com] 2013-12-11 20:40 Mistah_Darcy has quit [Ping timeout: 246 seconds] 2013-12-11 20:47 3'sd1 - 3'sd4 = 5 2013-12-11 20:47 https://www.destroyallsoftware.com/talks/wat 2013-12-11 20:56 ...what actually happens is that 4 is the sign bit in "3'sd4", which gets extended to -4 when the target is more than 3 bits. and it becomes 1 - (-4) = 5 2013-12-11 20:58 thus the rule: in verilog, when you want to represent the most negative integer, you should write its absolute (positive) value instead :) 2013-12-11 21:03 Mistah_Darcy has joined #m-labs 2013-12-11 21:11 Mistah_Darcy has quit [Read error: Connection reset by peer] 2013-12-11 21:11 Mistah_Darcy has joined #m-labs 2013-12-11 21:33 [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/d2s6Dg 2013-12-11 21:33 migen/master 135a4fe Sebastien Bourdeauducq: fhdl/verilog: fix representation of negative integers... 2013-12-11 21:36 rjo, your test passes now. -1'sd1 was 1 in Verilog :) 2013-12-11 21:40 lekernel: that's horrible ;) 2013-12-11 21:40 lekernel: thanks for looking into this. i didn't have the guts to dive that deep into verilog. 2013-12-11 21:41 mumptai has joined #m-labs 2013-12-11 21:43 lekernel: that means verilog does sign extend literal constants even when they do not have a "-" that would indicate their negativity? 2013-12-11 21:43 it sign-extends operands when the context is signed 2013-12-11 21:44 the signedness of the context is defined by the signedness of all operands 2013-12-11 21:44 and you can mark literal constants as signed by using 's 2013-12-11 21:45 in which case the MSB is the sign bit, and you have to set it manually - using the unary minus before the literal fails for the most negative integer, as we have seen :) 2013-12-11 21:46 you can also mark any part of an expression as signed by using $signed (Migen inserts those to provide better sign extension rules) 2013-12-11 21:51 lekernel: would writing -4'sd4 not work in a 3-bit signed context? 2013-12-11 21:53 it would work 2013-12-11 21:56 lekernel: would it not be more readable? 2013-12-11 21:56 but because that literal would make it a 4-bit context 2013-12-11 21:56 it would make it more readable, but then, it breaks the rule that literals use their minimum number of bits 2013-12-11 21:57 which can cause problems e.g. when putting them in Cat() or Replicate() 2013-12-11 21:58 btw, check out this horrible presentation http://www.sutherland-hdl.com/papers/2006-SNUG-Boston_standard_gotchas_presentation.pdf 2013-12-11 22:01 hey, it contains pixelated men and pretty colors ;) 2013-12-11 22:04 lekernel: ok. understood. but i dont see why verilog is unable to represent the most negative integer using a unary minus. i do understand why 3'sd4 is "wrong" in the sense that it either invalid or -4. But why is -3'sd4 not -4? Just because --3'sd4 != 3'sd4 then? 2013-12-11 22:04 because 3'sd4 is -4 2013-12-11 22:04 that presentation seriously lacks some WordArt and yellow text. 2013-12-11 22:05 as the 3rd bit (MSB) is the sign bit, which would have weight 4 if the value wasn't signed 2013-12-11 22:05 lekernel: wouldn't you want 3'sd4 to be invalid in a better world? 2013-12-11 22:06 yes, but then you can't represent -4, as the unary minus won't let you 2013-12-11 22:08 (you need an extra bit to represent the absolute value of the most negative integer) 2013-12-11 22:09 lekernel: hmm 2013-12-11 22:10 right now, migen spits out the explicit two's complement representation of the value, and tells Verilog to treat the MSB as sign bit 2013-12-11 22:11 it's a straightforward solution, which has the inconvenience of making negative values less readable in the generated code 2013-12-11 22:12 and you get things like 1'sd1 for -1, which is horrible, but works ... 2013-12-11 22:16 lekernel: so this is the only way to represent the most negative signed integer without wrongly increasing the bit-width of the context? 2013-12-11 22:17 sh4rm4 has quit [Ping timeout: 264 seconds] 2013-12-11 22:17 Mistah_Darcy_ has joined #m-labs 2013-12-11 22:17 mumptai has quit [Quit: Verlassend] 2013-12-11 22:18 I think so 2013-12-11 22:20 Mistah_Darcy has quit [Read error: Connection reset by peer] 2013-12-11 22:23 ah, no 2013-12-11 22:23 -1'd1 works 2013-12-11 22:23 :) 2013-12-11 22:24 sh4rm4 has joined #m-labs 2013-12-11 22:26 hmm, actually, I could have simply dropped the "s", since the unary minus also makes the context signed 2013-12-11 22:30 ah, no, it does not 2013-12-11 22:30 -1'd1*5'sd5 is 155 2013-12-11 22:30 1'sd1*5'sd5 is -5 as one would expect 2013-12-11 22:31 $signed(-1'd1)*5'sd5 also works 2013-12-11 22:31 but is quite heavy 2013-12-11 22:31 Verilog is such a terrible language o__O 2013-12-11 22:34 rjo, so, which is less bad? 2013-12-11 22:35 1) $signed(-'d) 2013-12-11 22:35 2) 'sd 2013-12-11 22:35 3) 'sd /* */ 2013-12-11 23:04 lekernel has quit [Quit: Leaving] 2013-12-12 00:51 lekernel: oh my. 2013-12-12 00:54 lekernel: i think the 2) that you implemented is probably good enough. especially since the representation of integers is not preserved anyway. everything becomes a decimal number. and the fact that they are now also always positive is not so much of an additional issue. 2013-12-12 02:07 xiangfu has joined #m-labs 2013-12-12 02:48 antgreen has joined #m-labs 2013-12-12 09:26 lekernel has joined #m-labs 2013-12-12 10:01 key2 has joined #m-labs 2013-12-12 11:07 Mistah_Darcy_ has quit [Read error: Connection reset by peer] 2013-12-12 12:33 antgreen has quit [Ping timeout: 246 seconds] 2013-12-12 14:23 key2 has quit [Ping timeout: 272 seconds] 2013-12-12 14:24 antgreen has joined #m-labs 2013-12-12 15:00 [misoc] sbourdeauducq pushed 1 new commit to master: http://git.io/t9AS2g 2013-12-12 15:00 misoc/master 9aa474c Sebastien Bourdeauducq: gitmodules: use https and m-labs 2013-12-12 15:04 azonenberg has joined #m-labs 2013-12-12 15:51 Scopeuk has joined #m-labs 2013-12-12 16:37 antgreen has quit [Ping timeout: 240 seconds] 2013-12-12 16:42 [migen] sbourdeauducq pushed 3 new commits to master: http://git.io/aPosUw 2013-12-12 16:42 migen/master adffec3 Sebastien Bourdeauducq: utils/misc: add gcd_multiple function to compute GCD or any number of integers 2013-12-12 16:42 migen/master adda930 Sebastien Bourdeauducq: fhdl/simplify: add FullMemoryWE decorator that splits memories to remove partial WEs 2013-12-12 16:42 migen/master c13fe1b Sebastien Bourdeauducq: specials/Memory: allow for more flexibility in memory port signals 2013-12-12 16:42 [misoc] sbourdeauducq pushed 1 new commit to master: http://git.io/EuMZvQ 2013-12-12 16:42 misoc/master 860f273 Sebastien Bourdeauducq: make: add decorator option 2013-12-12 17:52 hmm, yosys seems to hate initialized memories 2013-12-12 18:54 I think there was a post saying that he recently added support for this 2013-12-12 19:02 I removed them; now I get this 2013-12-12 19:02 26.9.5.1. Executing ABC. 2013-12-12 19:02 ABC: ABC command line: "read_verilog /tmp/yosys-abc-IuvjWB/input.v; read_lut /tmp/yosys-abc-IuvjWB/lutdefs.txt; strash; balance; dch; if; write_blif /tmp/yosys-abc-IuvjWB/output.blif". 2013-12-12 19:02 ABC: Warning: Performing LUT mapping with 4022 choices. 2013-12-12 19:02 ABC: 2013-12-12 19:02 ERROR: Syntax error in line 115! 2013-12-12 19:03 line 115 of input.v is just 2013-12-12 19:03 wire n113; // $add$/home/sb/M-Labs/misoc/verilog/lm32/submodule/rtl/lm32_cpu.v:1573$1511.alu.V[24].adder.t2 2013-12-12 19:03 there are many similar ones before that don't seem to cause problems 2013-12-12 19:03 but I'm perhaps looking at the wrong file 2013-12-12 19:04 yep, that was the thing I was talking about 2013-12-12 19:04 the max line length for blif files is 4096 2013-12-12 19:04 ah, did you investigate? 2013-12-12 19:04 in his parser 2013-12-12 19:05 probably worth emailing him, he fixed the lm32 problems in a couple days 2013-12-12 19:05 well, except that one perhaps 2013-12-12 19:05 I actually started rewriting the parser 2013-12-12 19:05 to be token based rather than line based 2013-12-12 19:07 but writing parsers in C is always so annoying 2013-12-12 19:30 larsc_, do you have any workaround? 2013-12-12 19:38 increase the buffer size in passes/abc/blifparse.cc 2013-12-12 20:06 mumptai has joined #m-labs 2013-12-12 20:44 wow, it produced a misoc netlist 2013-12-12 20:44 but then 2013-12-12 20:44 ERROR:NgdBuild:196 - On or above line 906729 in file "simplesoc-mixxeo.edif": 2013-12-12 20:44 Problem parsing "rename". This likely means that the EDIF netlist was 2013-12-12 20:44 improperly written. Please contact the vendor of the program that produced 2013-12-12 20:44 this EDIF. 2013-12-12 20:45 'line 906729' 2013-12-12 20:45 that's a big file 2013-12-12 20:45 yeh :) 2013-12-12 20:45 it took a lot of time to produce, too 2013-12-12 20:45 I think it's unreasonable to expect it would work 2013-12-12 20:46 87MB 2013-12-12 20:46 the cache probably takes up quite a bit of space considering the is no bram or dram support 2013-12-12 21:14 what are those? http://www.xilinx.com/products/silicon-devices/fpga/kintex-ultrascale/index.htm 2013-12-12 21:14 "ASIC-like clocking" - did they finally manage to make FPGAs that are not slow? 2013-12-12 21:14 lekernel: at the moment? merely warm vapour exhaled by marketing people. 2013-12-12 21:15 Apparently 'Kintex Ultrascale' is their new stupid name for '8'-series parts 2013-12-12 21:15 yeah, it smells a lot of that 2013-12-12 21:15 (given that the whole 7 lineup isn't shipping yet, I figure its still 3 years off) 2013-12-12 21:18 yea, I think it's just marketing bs 2013-12-12 21:18 by asic-like-clocking, they probably mean "actually working clock gating" or something else 2013-12-12 21:18 yes 2013-12-12 21:19 so you can save power 2013-12-12 21:19 er, wait "not-explicitely-marked-as-broken-but-still-broken-anyways clock gating" 2013-12-12 21:19 Just like dynamic reconfig in S3 + S6 series... 2013-12-12 21:20 it says "ASIC-like clocking for scalability, performance and lower dynamic power" :) 2013-12-12 21:20 well, maybe they mean the performance of a 1995 ASIC or something 2013-12-12 21:21 they probably don't mean anything by it, it just sounds good ;) 2013-12-12 21:22 lekernel: if you want ASIC-like performance in an FPGA, I'll sell you one! (while the FPGA achieves ASIC-like performance + power consumption, the builtin 1-ton FIB used for reconfiguration uses slightly more. It also takes 6 months to reconfigure the design) 2013-12-12 21:28 barmstrong has joined #m-labs 2013-12-12 22:03 Mistah_Darcy has joined #m-labs 2013-12-12 22:22 [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/OThtHg 2013-12-12 22:22 migen/master 3196462 Sebastien Bourdeauducq: add support for Verilog include paths 2013-12-12 22:22 [misoc] sbourdeauducq pushed 2 new commits to master: http://git.io/hUN8wA 2013-12-12 22:22 misoc/master c95b9d6 Sebastien Bourdeauducq: gensoc: use add_verilog_include_path 2013-12-12 22:22 misoc/master ba46cd3 Sebastien Bourdeauducq: make.py: update description 2013-12-12 22:39 Scopeuk is now known as Scopeuk-AFK 2013-12-12 23:07 [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/CAdaTw 2013-12-12 23:07 migen/master a20688f Sebastien Bourdeauducq: fhdl/simplify/FullMemoryWE: fix WE slice for multi-port mems 2013-12-12 23:25 lekernel has quit [Quit: Leaving] 2013-12-12 23:38 mumptai has quit [Quit: Verlassend] 2013-12-13 00:03 antgreen has joined #m-labs 2013-12-13 01:09 mrueg has quit [Remote host closed the connection] 2013-12-13 01:59 mrueg has joined #m-labs 2013-12-13 05:35 kyak has joined #m-labs 2013-12-13 09:01 lekernel has joined #m-labs 2013-12-13 12:58 antgreen has quit [Ping timeout: 272 seconds] 2013-12-13 13:12 antgreen has joined #m-labs 2013-12-13 14:07 antgreen has quit [Ping timeout: 252 seconds] 2013-12-13 14:09 https://www.gnu.org/software/automake/manual/html_node/Nested-Packages.html 2013-12-13 14:09 "Autoconfiscated packages (that means packages whose build system have been created by Autoconf and friends) " 2013-12-13 14:17 xiangfu has quit [Ping timeout: 250 seconds] 2013-12-13 14:18 xiangfu has joined #m-labs 2013-12-13 14:23 antgreen has joined #m-labs 2013-12-13 14:39 autoconfiscated 2013-12-13 14:39 lol 2013-12-13 14:41 Ultrascale is indeed 8 series 2013-12-13 14:41 I predict they'll invent another name for 9 series 2013-12-13 14:41 then 10 series will be X series 2013-12-13 14:41 7 is 28nm, 8/U is 20nm 2013-12-13 14:41 so 9 series will be 16nm finfet 2013-12-13 14:42 and X series will be 14/11nm? 2013-12-13 14:42 xilinx is definitely embracing 2.5/3D, i wonder when we'll see it trickle down from the ultra-high-end to midrange and low end parts 2013-12-13 14:46 antgreen has quit [Ping timeout: 246 seconds] 2013-12-13 16:44 proppy has joined #m-labs 2013-12-13 17:05 robmyers has joined #m-labs 2013-12-13 17:55 Gurty has joined #m-labs 2013-12-13 18:01 mumptai has joined #m-labs 2013-12-13 18:16 lekernel has quit [Quit: Leaving] 2013-12-13 18:51 Alarm has joined #m-labs 2013-12-13 19:15 Alarm has quit [Ping timeout: 252 seconds] 2013-12-13 19:19 Alarm has joined #m-labs 2013-12-13 19:32 Alarm has quit [Ping timeout: 252 seconds] 2013-12-13 19:43 Alarm has joined #m-labs 2013-12-13 20:04 antgreen has joined #m-labs 2013-12-13 20:24 Alarm has quit [Quit: ChatZilla 0.9.90.1 [Firefox 25.0.1/20131112160018]] 2013-12-13 20:24 Alarm has joined #m-labs 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joined #m-labs 2013-12-15 11:47 xiangfu has quit [Ping timeout: 240 seconds] 2013-12-15 11:49 xiangfu has joined #m-labs 2013-12-15 12:22 lekernel has joined #m-labs 2013-12-15 12:25 kyak has joined #m-labs 2013-12-15 14:01 qwebirc51049 has joined #m-labs 2013-12-15 14:05 qwebirc51049 has quit [Ping timeout: 272 seconds] 2013-12-15 14:12 lo 2013-12-15 14:15 hi 2013-12-15 14:27 lekernel: When I get some time I will try to see how to adapt the nexys 3 port to integrate better with MiSoC Migen Mibuild new organization 2013-12-15 14:27 but it's not very high on my priority list ^^ 2013-12-15 14:28 that would be a reason to play a little bit more with Migen stuff 2013-12-15 14:28 I don't even have the board, but rkujawa has one and I can SSH to his machine 2013-12-15 15:33 kilae has joined #m-labs 2013-12-15 16:34 mumptai has quit [Quit: Verlassend] 2013-12-15 16:39 mumptai has joined #m-labs 2013-12-15 17:40 lekernel: There? 2013-12-15 17:41 yes 2013-12-15 17:41 lekernel: The new case looks very nice 2013-12-15 17:41 case/rendering 2013-12-15 17:41 Looks awesome 2013-12-15 17:42 :) 2013-12-15 17:43 lekernel: Is it a rendering or a real case? 2013-12-15 17:43 it's a rendering 2013-12-15 17:44 lekernel: I'll be happy to help make parts if it would help the cause 2013-12-15 17:44 figuring out how to fab it in an expensive (as opposed to horribly expensive) way atm 2013-12-15 17:45 lekernel: I have mills/lathes/3d printers/laser cutters. I can probably help 2013-12-15 17:45 nice, thanks :) 2013-12-15 17:45 have you made other cases before? 2013-12-15 17:45 Its probably one of the few ways I can help the project :) 2013-12-15 17:46 lekernel: I have made cases for reprap stuff, and for some FPGAs 2013-12-15 17:47 hmm, to be honest, reprap stuff is way below what I need 2013-12-15 17:47 what's the FPGA stuff? 2013-12-15 17:47 I've made some lasercut cases for the papilio. 2013-12-15 17:47 lekernel: I couldn't make all the ones you need. But I could help you design/prototype 2013-12-15 17:48 lekernel: Just offering to help. If you don't need/want it, thats ok too 2013-12-15 17:48 :) 2013-12-15 17:50 lekernel: I usually use my repraps or mills to prototype things. If it works well, then I'll get it manufactured 2013-12-15 17:50 well, I definitely appreciate the offer :) but well, it's not an easy project 2013-12-15 17:51 lekernel: I typically use solidworks (real license :P ) for designing 2013-12-15 17:51 it'll be CNC milled aluminum by the way 2013-12-15 17:51 black anodized 2013-12-15 17:51 lekernel: What are the dimensions? 2013-12-15 17:51 and glass 2013-12-15 17:51 approximate 2013-12-15 17:52 163x163mm 2013-12-15 17:52 height TBD... but the rendering is approximately to scale 2013-12-15 17:53 lekernel: Cool. I may try to mill it 2013-12-15 17:54 what method do you envision? 2013-12-15 17:54 method? 2013-12-15 17:55 what type of piece you start the milling with, for example 2013-12-15 17:55 plain block of aluminum? bent sheets? etc. 2013-12-15 17:57 Well, one block of alu would be pretty expensive for machine time 2013-12-15 17:57 It would be pretty easy (and relatively cheap) to do 6 3-6mm plates 2013-12-15 17:58 how do you make sure they always fit perfectly together, considering the manufacturing tolerances? 2013-12-15 17:58 If you want to do bent plates, I have a friend that can get that done + powder coating pretty cheap 2013-12-15 17:58 and how do you assemble those 6 plates? 2013-12-15 17:59 lekernel: Oh, I use solidworks to design it. It guarantees the model fits together 2013-12-15 17:59 lekernel: I would probably tap the edges and use some m3 screws 2013-12-15 17:59 how does it guarantee that? 2013-12-15 18:00 Because you put all the parts together in an assembly 2013-12-15 18:00 It makes sure all the dimensions line up 2013-12-15 18:00 Then when you machine it you use the model 2013-12-15 18:00 sure, but if one of the plates is a fraction of a mm off, then you get a hole in the case 2013-12-15 18:00 and if it's too large, it doesn't fit 2013-12-15 18:01 so no, solidworks doesn't guarantee your assembly fits :-) 2013-12-15 18:01 lekernel: Well, solidworks ensures the model is good. I pull the parts into a cam program which ouputs the gcode 2013-12-15 18:02 And my mill operates on the gcode. 2013-12-15 18:02 yes, and that mill isn't perfectly precise 2013-12-15 18:03 The mill is accurate to .0127mm across a 304mm span 2013-12-15 18:03 So the tolerance is reasonably tight. 2013-12-15 18:03 But like I said, I use my stuff to prototype, not for full manufacturing. 2013-12-15 18:10 os1r1s, I can send you the full CAD data if you want to play around 2013-12-15 18:11 os1r1s, but I have to say, I'm looking for an experienced mechanical engineer who's going to deliver a perfect case all the way to series manufacturing 2013-12-15 18:12 I have several other projects in parallel, and little time to deal with any mess coming from the case mfging... 2013-12-15 18:13 and I want something you could put in a Apple store without feeling ashamed 2013-12-15 18:17 lekernel: Ahh, ok. Gotcha. 2013-12-15 18:19 lekernel: for that, you need an apple logo and either a time machine or a necromancer :) 2013-12-15 18:20 os1r1s: you seem so have a nice collection of tools. the mills, now many axes ? also, do you make molds or just mill the models directly ? 2013-12-15 18:21 wpwrak: They are small ones for the most part. The one I use most often has 4 axes, but I have plans to add a 5th 2013-12-15 18:21 lekernel: (making parts fit) i suppose also with high-end equipment, the process is basically: a) make a model that's a good as can be, b) make it, c) see where reality and theory don't quite agree, d) add tweaks to the model (or add post-processing steps), back to b) 2013-12-15 18:22 wpwrak: I typically just mill whatever I want done. Its not a production shop by any means. Its just my personal stuff 2013-12-15 18:22 4 axes is already very nice. wish my little 3 axis mill had that ... 2013-12-15 18:23 yeah, same here 2013-12-15 18:23 wpwrak: I have one that I use for metal (4 axis), one I use for PCBs, and one I use for wood/plastic (gantry router). 2013-12-15 18:24 that's a very nice collection indeed 2013-12-15 18:24 wpwrak: thx 2013-12-15 18:49 Aha! lekernel is going to sell the Mixxeo at the apple stores, I knew it! 2013-12-15 18:49 ;) 2013-12-15 18:49 his move from gcc to clang rang a bell, now I can see the bigger picture :p 2013-12-15 18:51 haha, no way, but enough of oshw with mediocre design =] 2013-12-15 18:52 I agree! 2013-12-15 18:53 is the screen touch sensitive? 2013-12-15 19:38 Alarm_ has joined #m-labs 2013-12-15 19:39 Alarm has quit [Ping timeout: 264 seconds] 2013-12-15 19:39 Alarm_ is now known as Alarm 2013-12-15 19:52 antgreen has quit [Ping timeout: 252 seconds] 2013-12-15 20:48 antgreen has joined #m-labs 2013-12-15 20:51 Scopeuk-AFK is now known as Scopeuk 2013-12-15 20:55 no, but the blend mode lights are 2013-12-15 21:20 "Touch the light !" 2013-12-15 21:21 of course, only as long as it isn't blue: http://en.wikipedia.org/wiki/Goi%C3%A2nia_accident 2013-12-15 21:35 kilae has quit [Quit: ChatZilla 0.9.90.1 [Firefox 25.0.1/20131112160018]] 2013-12-15 21:59 Alarm has quit [Remote host closed the connection] 2013-12-15 22:12 Scopeuk is now known as Scopeuk-AFK 2013-12-15 22:48 kyak has quit [Ping timeout: 248 seconds] 2013-12-15 22:49 kyak has joined #m-labs 2013-12-15 22:49 kyak has joined #m-labs 2013-12-15 22:49 kyak has quit [Changing host] 2013-12-15 23:13 lekernel has quit [Quit: Leaving] 2013-12-15 23:50 kuevda has joined #m-labs 2013-12-15 23:53 kuevda has quit [Read error: Connection reset by peer] 2013-12-16 01:35 mumptai has quit [Ping timeout: 260 seconds] 2013-12-16 01:51 antgreen_ has joined #m-labs 2013-12-16 01:53 antgreen has quit [Ping timeout: 252 seconds] 2013-12-16 07:09 wpwrak has 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ducks the debris 2013-12-17 15:42 Mistah_Darcy_ has joined #m-labs 2013-12-17 15:45 Mistah_Darcy has quit [Ping timeout: 260 seconds] 2013-12-17 16:05 Mistah_Darcy_ has quit [Read error: Connection reset by peer] 2013-12-17 16:06 Mistah_Darcy_ has joined #m-labs 2013-12-17 16:53 antgreen_ has quit [Remote host closed the connection] 2013-12-17 17:05 antgreen has joined #m-labs 2013-12-17 17:55 [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/-VhEwQ 2013-12-17 17:55 migen/master be1c855 Robert Jordens: migen/fhdl/tools: speed up group_by_targets (halves the mixxeo runtime) 2013-12-17 18:34 _whitelogger has joined #m-labs 2013-12-17 19:15 wpwrak: next report from the statistics department will be full of joy and funny puns I hope :D 2013-12-17 19:46 i think this time milkymist may even beat qi-hw ;-) 2013-12-17 20:14 sh4rm4 is now known as Jarrett 2013-12-17 20:15 Jarrett is now known as sh4rm4 2013-12-17 20:28 ahah I don't think so :p 2013-12-17 20:28 you're flooding too much with anelok ;) 2013-12-17 20:28 (kidding) 2013-12-17 20:44 * wpwrak checks the archives 2013-12-17 20:45 qi-hw: 21 kB, milkymist/m-lab: 19 kB. 2013-12-17 20:47 damn it, it's close :) 2013-12-17 20:47 * ysionneau opens a new mail editor 2013-12-17 21:33 zahmuh has joined #m-labs 2013-12-17 21:41 zahmuh has quit [K-Lined] 2013-12-17 21:42 kvaksha has joined #m-labs 2013-12-17 21:51 kvaksha has quit [Ping timeout: 240 seconds] 2013-12-17 23:16 mumptai has quit [Ping timeout: 250 seconds] 2013-12-17 23:21 ysionneau has quit [Ping timeout: 245 seconds] 2013-12-17 23:21 ysionneau has joined #m-labs 2013-12-17 23:53 lekernel has quit [Ping timeout: 250 seconds] 2013-12-18 02:37 kristianpaul has quit [Ping timeout: 245 seconds] 2013-12-18 02:39 kristianpaul has joined #m-labs 2013-12-18 02:46 kristianpaul has quit [Quit: Reconnecting] 2013-12-18 02:46 kristianpaul has joined #m-labs 2013-12-18 07:23 Gurty has quit [Read error: Connection reset by peer] 2013-12-18 07:35 Gurty has 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10:12 popo has quit [Ping timeout: 240 seconds] 2013-12-19 10:13 qwebirc88278 has quit [Ping timeout: 272 seconds] 2013-12-19 10:19 hi popo` 2013-12-19 10:27 _florent_ has joined #m-labs 2013-12-19 10:55 <_florent_> Hi ex-milkymisters :) 2013-12-19 10:55 <_florent_> I'm just trying to catch up with the last migen/misoc changes 2013-12-19 10:55 <_florent_> and was wondering: 2013-12-19 10:56 <_florent_> will you be ok to integrate some "unofficial" ports in MiSoC? 2013-12-19 10:56 <_florent_> I'm thinking of the de0-nano port in a first time 2013-12-19 10:57 <_florent_> or do you prefer that the "unofficials" ports live outside of MiSoC? 2013-12-19 10:57 <_florent_> The good thing I see with the de0-nano port is that is demonstrates the use of the altera toolchain 2013-12-19 10:58 <_florent_> and will only need the c4sdrphy to be added to MiSoC 2013-12-19 10:59 <_florent_> BTW does the LX9 port dissapeared? I don't see it in MiSoC and I'm not able to find the lx9 port on Robert's Github? 2013-12-19 11:06 yes, we can have the de0-nano port in misoc, but it needs to work and keep working :) 2013-12-19 11:08 <_florent_> yes of course I will do the work needed to integrate it correctly 2013-12-19 11:08 <_florent_> and maintain it 2013-12-19 11:09 <_florent_> It's basically only the "simple" SoC plus the c4sdrphy 2013-12-19 11:10 <_florent_> I'll work on it and let you now it's ready 2013-12-19 11:11 <_florent_> I'm also thinking of re-trying the Vivado support I've made some time ago for the KC705 port 2013-12-19 11:12 <_florent_> (Vivado was not able to finish the P&R the last time I tried) 2013-12-19 11:12 <_florent_> Are you interested by the Vivado port? 2013-12-19 11:15 did you clean up the KC705 DDR3 PHY? 2013-12-19 11:16 <_florent_> no, for now it's not cleaned up, but I will that soon and try to integrate it in MiSoC in case you want to integrate it 2013-12-19 11:16 <_florent_> will do that 2013-12-19 11:17 what I mean by "cleaned up" is do the read/write leveling properly 2013-12-19 11:17 I doubt your solution is stable across PVT 2013-12-19 11:18 I had a look at DDR3 datasheets, and the timing numbers don't check out 2013-12-19 11:21 <_florent_> I will maybe also try the other solution (with the trick on the controller and without read-leveling) 2013-12-19 11:23 "read leveling" is use DQS :) DDR3 has a comparatively large tolerance on the clock-to-DQS timing 2013-12-19 11:24 if you sample data with the clock, like you can do with previous DDR generations, you can only use it reliably at DDR/DDR2 performance levels, maybe worse 2013-12-19 11:27 and you should not use fully asynchronous FIFOs clocked by DQS, as those introduce a large and unpredictable latency. you should write the FIFO with DQS and read it with the clock in the cycle that will sample the correct data and not cause setup/hold violations in the worst case (slowest) DQS arrival time 2013-12-19 11:27 (that cycle is fixed after the issue of a read command to the DDR3) 2013-12-19 11:31 <_florent_> ok thanks for the informations 2013-12-19 11:31 <_florent_> I really want to try this solution 2013-12-19 11:31 <_florent_> the thing is with DDR, you know when you start, but you really don't know when you'll have something that works :) 2013-12-19 11:32 the "trick" in the controller is to issue a dummy read command (i.e. repeat it) when there is a bubble, in order to flush data out of the IDDR2 and into the FIFO 2013-12-19 11:32 <_florent_> and you don't have anything the see what is going wrong (except if you work for big compagnies :() 2013-12-19 11:33 alternative is not to use the IDDR2 and design a soft dual-edge-clocked FIFO, but it sounds much more difficult, less portable, easier to get wrong, and possibly slower 2013-12-19 11:36 <_florent_> it will probably be easier to use the IDDR2 in a first time since detecting bubble should be relatively easy 2013-12-19 11:38 yes. soft async logic in FPGAs is a lot of pain: the routing has a lot of skew and the software tools aren't made for that (nor the FPGA architecture). plus you want that to be fast ... 2013-12-19 11:44 <_florent_> yes that's why they added in_fifo / out_fifo / phasers but since it is not documented, it's maybe even easier to use soft async logic ;) 2013-12-19 11:46 the xilinx design is horrible, don't touch it 2013-12-19 11:50 <_florent_> thanks for the warning but I was not going to touch it :)I'm not going to touch it 2013-12-19 11:50 <_florent_> oops 2013-12-19 13:17 _franck_web_ has joined #m-labs 2013-12-19 14:09 antgreen has quit [Ping timeout: 245 seconds] 2013-12-19 14:09 _florent_ has quit [Ping timeout: 272 seconds] 2013-12-19 15:06 lekernel has quit [Ping timeout: 250 seconds] 2013-12-19 15:11 aeris has quit [Quit: en a pas] 2013-12-19 15:18 aeris has joined #m-labs 2013-12-19 15:21 lekernel has joined #m-labs 2013-12-19 16:03 lekernel has quit [Remote host closed the connection] 2013-12-19 16:04 lekernel has joined #m-labs 2013-12-19 16:05 antgreen has joined #m-labs 2013-12-19 16:52 antgreen has quit [*.net *.split] 2013-12-19 16:55 antgreen has joined #m-labs 2013-12-19 16:58 antgreen has quit [*.net *.split] 2013-12-19 17:04 antgreen has joined #m-labs 2013-12-19 17:06 _franck_web_ has quit [Quit: Page closed] 2013-12-19 17:09 antgreen has quit [*.net *.split] 2013-12-19 17:15 antgreen has joined #m-labs 2013-12-19 17:30 lekernel: Xilinx apparently doesnt like documenting any of their memory interface hard IP 2013-12-19 17:30 They seem to assume you'll use MIG if you use memory at all 2013-12-19 17:30 or should i say, they're pushing MIG 2013-12-19 17:32 ...and its non-portability :) 2013-12-19 17:32 Indeed 2013-12-19 17:32 plus horrid interface etc. 2013-12-19 17:33 (GUI) 2013-12-19 17:34 popo` has quit [Ping timeout: 252 seconds] 2013-12-19 18:02 antgreen has quit [Read error: Operation timed out] 2013-12-19 18:19 antgreen has joined #m-labs 2013-12-19 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23:21 sh4rm4 has quit [Quit: sh4rm4] 2013-12-20 23:22 sh[4]rm4 has joined #m-labs 2013-12-20 23:22 sh[4]rm4 has quit [Remote host closed the connection] 2013-12-20 23:23 sh4rm4 has joined #m-labs 2013-12-21 00:05 mumptai has quit [Ping timeout: 240 seconds] 2013-12-21 00:40 Mistah_Darcy has joined #m-labs 2013-12-21 03:33 antgreen has joined #m-labs 2013-12-21 04:58 Mistah_Darcy has quit [Read error: Connection reset by peer] 2013-12-21 04:58 Mistah_Darcy has joined #m-labs 2013-12-21 07:24 wpwrak has quit [Ping timeout: 264 seconds] 2013-12-21 07:30 playthatbeat has quit [Ping timeout: 252 seconds] 2013-12-21 09:05 jaeckel has quit [Ping timeout: 245 seconds] 2013-12-21 09:18 jaeckel has joined #m-labs 2013-12-21 09:39 mumptai has joined #m-labs 2013-12-21 11:24 wpwrak has joined #m-labs 2013-12-21 12:32 playthatbeat has joined #m-labs 2013-12-21 12:49 xiangfu has quit [Remote host closed the connection] 2013-12-21 13:00 mumptai has quit [Ping timeout: 245 seconds] 2013-12-21 13:06 Alarm has joined #m-labs 2013-12-21 13:56 playthatbeat has quit [Quit: KVIrc 4.2.0 Equilibrium http://www.kvirc.net/] 2013-12-21 13:59 playthatbeat has joined #m-labs 2013-12-21 14:50 antgreen has quit [Ping timeout: 248 seconds] 2013-12-21 14:54 sh4rm4 has quit [Remote host closed the connection] 2013-12-21 14:56 sh4rm4 has joined #m-labs 2013-12-21 15:06 antgreen has joined #m-labs 2013-12-21 15:20 sb0 has joined #m-labs 2013-12-21 16:28 sb0 has quit [Quit: Leaving] 2013-12-21 17:00 kristianpaul has quit [Quit: leaving] 2013-12-21 17:01 kristianpaul has joined #m-labs 2013-12-21 17:13 sh4rm4 has quit [Remote host closed the connection] 2013-12-21 17:15 sh4rm4 has joined #m-labs 2013-12-21 17:55 Alarm has quit [Read error: Connection reset by peer] 2013-12-21 18:04 mumptai has joined #m-labs 2013-12-21 19:30 Alarm has joined #m-labs 2013-12-21 19:34 I just discovered a bug in lm32 gcc: http://pastie.org/8568281 2013-12-21 19:35 notice how the (64-bit) double is passed on the stack from main, but read (partially) from r8 in var_arg_f 2013-12-21 19:37 the reason is that the lm32 abi doesn't split arguments between regs and stack, but the generic vararg handler in gcc can't handle that 2013-12-21 19:37 that's at least how I understand it 2013-12-21 19:40 I'm pretty sure that this is not lm32 specific problem 2013-12-21 19:40 so I suspect there is some support for this in gcc 2013-12-21 19:42 I actually stumbled on this when noticing the same bug in another (out of tree) backend that has the same ABI (not splitting args between regs and stack) 2013-12-21 19:42 I think most other archs do split args 2013-12-21 19:43 at least all other I have seen, that's why I wanted to find out how lm32 handles it... but it doesn't 2013-12-21 19:43 I might be mistaken by thing that some require that a 64-bit value must be aligned to even register numbers 2013-12-21 19:44 think 2013-12-21 19:44 I guess it's solveable, but I wonder how easily (writing your own vararg handler is what comes to mind) 2013-12-21 20:16 but we probably already specify somehwere that gcc should not split args between stack and regs when generating the code 2013-12-21 20:16 just looking at the same define in the default stdarg handler should do it I gues 2013-12-21 20:16 s 2013-12-21 20:19 yes, it's specified by not (re)defining TARGET_ARG_PARTIAL_BYTES 2013-12-21 20:19 the default hook is a function that return 0 2013-12-21 21:55 Alarm has quit [Remote host closed the connection] 2013-12-21 22:08 azonenberg has quit [Excess Flood] 2013-12-21 22:10 azonenberg has joined #m-labs 2013-12-21 23:24 mumptai has quit [Quit: Verlassend] 2013-12-21 23:33 antgreen has quit [Ping timeout: 264 seconds] 2013-12-21 23:36 antgreen has joined #m-labs 2013-12-21 23:51 antgreen has quit [Ping timeout: 246 seconds] 2013-12-22 08:59 mumptai has joined #m-labs 2013-12-22 10:01 mumptai has quit [Quit: Verlassend] 2013-12-22 11:15 aeris has quit [Read error: Connection reset by peer] 2013-12-22 11:15 aeris has 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antgreen_ has joined #m-labs 2013-12-26 15:38 antgreen has quit [Ping timeout: 240 seconds] 2013-12-26 17:02 antgreen_ has quit [Ping timeout: 272 seconds] 2013-12-26 17:08 antgreen_ has joined #m-labs 2013-12-26 19:26 larsc_ is now known as larsc 2013-12-26 19:47 antgreen_ has quit [Ping timeout: 272 seconds] 2013-12-26 19:54 mumptai has joined #m-labs 2013-12-26 23:10 mumptai has quit [Quit: Verlassend] 2013-12-27 01:16 key2 has quit [Quit: http://www.kiwiirc.com/ - A hand crafted IRC client] 2013-12-27 01:17 key2 has joined #m-labs 2013-12-27 01:21 key2 has quit [Client Quit] 2013-12-27 01:47 antgreen has joined #m-labs 2013-12-27 01:51 gric has quit [Quit: leaving] 2013-12-27 01:57 gric has joined #m-labs 2013-12-27 03:54 antgreen has quit [Quit: Leaving] 2013-12-27 04:29 wpwrak_ has quit [Ping timeout: 240 seconds] 2013-12-27 04:29 wpwrak_ has joined #m-labs 2013-12-27 04:30 gric has quit [Ping timeout: 240 seconds] 2013-12-27 04:30 gric has joined #m-labs 2013-12-27 04:36 antgreen has joined #m-labs 2013-12-27 05:52 wpwrak_ has quit [Ping timeout: 245 seconds] 2013-12-27 05:59 Thorn has quit [Read error: No route to host] 2013-12-27 06:00 Thorn has joined #m-labs 2013-12-27 06:00 Thorn has joined #m-labs 2013-12-27 06:00 Thorn has quit [Changing host] 2013-12-27 06:04 [florian1 has quit [Remote host closed the connection] 2013-12-27 06:10 [florian] has joined #m-labs 2013-12-27 06:10 [florian] has joined #m-labs 2013-12-27 06:10 [florian] has quit [Changing host] 2013-12-27 07:35 Scopeuk_ has joined #m-labs 2013-12-27 07:35 kristian1aul has joined #m-labs 2013-12-27 07:42 Scopeuk has quit [*.net *.split] 2013-12-27 07:42 kristianpaul has quit [*.net *.split] 2013-12-27 08:04 wpwrak has joined #m-labs 2013-12-27 10:56 sb0 has joined #m-labs 2013-12-27 10:56 hi 2013-12-27 10:56 * sb0 is in Warsaw 2013-12-27 12:18 visiting creotech [sp?] ? 2013-12-27 12:29 * larsc is in hamburg 2013-12-27 12:29 anybody else at the c3? 2013-12-27 12:48 wpwrak, maybe, but mostly friends and labs 2013-12-27 12:48 larsc, did you see EHSM posters? 2013-12-27 13:28 mumptai has joined #m-labs 2013-12-27 13:55 wpwrak has quit [Ping timeout: 272 seconds] 2013-12-27 13:57 sb0: not yet 2013-12-27 13:58 but I think I didn't see any posters at all 2013-12-27 15:52 wpwrak has joined #m-labs 2013-12-27 16:45 xiangfu has quit [Ping timeout: 252 seconds] 2013-12-27 16:47 xiangfu has joined #m-labs 2013-12-27 18:37 sb0_ has joined #m-labs 2013-12-27 18:40 sb0 has quit [Ping timeout: 252 seconds] 2013-12-27 21:37 xiangfu has quit [Ping timeout: 260 seconds] 2013-12-27 21:38 xiangfu has joined #m-labs 2013-12-27 23:21 mumptai has quit [Quit: Verlassend] 2013-12-27 23:56 balrog has joined #m-labs 2013-12-28 00:04 sb0_ has quit [Quit: Leaving] 2013-12-28 00:25 balrog has quit [Ping timeout: 272 seconds] 2013-12-28 00:34 balrog has joined #m-labs 2013-12-28 03:55 JewFro297 has joined #m-labs 2013-12-28 03:55 Sup? 2013-12-28 04:00 I'm working on designing an 80186 compatible computer on the DE0 2013-12-28 05:24 JewFro297 has quit [Ping timeout: 240 seconds] 2013-12-28 08:00 sh4rm4 has quit [Ping timeout: 264 seconds] 2013-12-28 11:40 sh4rm4 has joined #m-labs 2013-12-28 12:04 sb0 has joined #m-labs 2013-12-28 12:53 jix has joined #m-labs 2013-12-28 14:14 JewFro297 has joined #m-labs 2013-12-28 15:22 JewFro297: Hi! 2013-12-28 15:23 Sup? 2013-12-28 15:23 What will be the purpose of your project? 2013-12-28 15:23 It's just for fun, a learning experience type thing 2013-12-28 15:23 I mean, you need this old 80186 for something? 2013-12-28 15:24 ah ok, good :) 2013-12-28 15:24 Nah I have a 486 machine in my basement that still runs 2013-12-28 15:24 I throw mine out a few years ago 2013-12-28 15:24 I just kept the CPU 2013-12-28 15:24 Shoulda sold it, they're worth a good amount to collectors 2013-12-28 15:24 really? 2013-12-28 15:25 it was taking a lot of space for nothing 2013-12-28 15:25 Well, back when I was looking up how much it would cost for a new motherboard I was seeing $1000 2013-12-28 15:25 I had 3 old computers taking hell of a place 2013-12-28 15:25 I dumped everything except CPUs 2013-12-28 15:25 I don't think they sell for that much though 2013-12-28 15:25 because it's rare I think 2013-12-28 15:25 http://www.ebay.com/itm/IBM-PS-2-Model-56-S-C-Powers-On-For-Parts-Or-Repair-Listing-2-/400632728531 2013-12-28 15:26 Looks like they aren't, oh well 2013-12-28 15:26 good luck then with your project 2013-12-28 15:26 Are you gonna do it in Verilog? VHDL? Migen (python) 2013-12-28 15:26 ? 2013-12-28 15:27 Verilog 2013-12-28 15:28 I've never heard about Migen 2013-12-28 15:28 (Off to google...) 2013-12-28 15:29 it's a python framework for designing digital logic 2013-12-28 15:29 it's been used to design a System-on-Chip for instance 2013-12-28 15:30 it has nice helpers for generating bus signals, arbiters, connecting cores together 2013-12-28 15:30 Looks interesting, it seems sort of like a high level hardware language 2013-12-28 15:31 if you have questions about it sb0 here (sometimes his nickname is "lekernel") developped Migen 2013-12-28 15:31 yes, high level, tries to do the boring stuff for you 2013-12-28 15:31 Cool, I'll probably check it out sometime 2013-12-28 15:32 documentation is out there: http://milkymist.org/3/migen.html 2013-12-28 15:32 it supports dataflow paradigm 2013-12-28 15:32 I let you check the doc out :) 2013-12-28 15:36 Pretty cool, do you know if it 2013-12-28 15:36 's used in the industry at all? 2013-12-28 15:53 it's used by some research lab AFAIK 2013-12-28 15:57 a presentation about it https://www.youtube.com/watch?v=yxKMsAi_WEA&noredirect=1 2013-12-28 16:04 Is the speaker sb0? 2013-12-28 17:02 yes 2013-12-28 17:31 sh4rm4 has quit [Remote host closed the connection] 2013-12-28 17:48 sh4rm4 has joined #m-labs 2013-12-28 18:01 mwalle: after investigation, the psw gets reset from 0xC3 to 0x03 during the call to splash_display() 2013-12-28 18:02 so most certainly a dtlb miss :o 2013-12-28 18:02 what's weird is that dtlb miss occure before that, because the 0x43 turns into 0xC3 2013-12-28 18:03 (edtlbe is set) 2013-12-28 18:05 more precisely it's due to the loop which copies the splash_screen from the flash memory to the main memory (framebuffer) 2013-12-28 18:09 or maybe it means somehow I get a double dtlb miss ... which would overwrite edtlbe with dtlbe (which is 0 inside the exception handler) 2013-12-28 18:09 but it should be impossible to get this double dtlb miss 2013-12-28 18:12 maybe there is an issue if I have 2 load-stores in a row 2013-12-28 18:12 and the first causes a dtlb exception 2013-12-28 18:12 maybe the second one causes an exception too ... 2013-12-28 18:20 turns out it's not the issue: in simulation, 2 loads in a row only triggers the exception handler once and edtlbe is not overwritten 2013-12-28 18:37 sb0_ has joined #m-labs 2013-12-28 18:41 sb0 has quit [Ping timeout: 252 seconds] 2013-12-28 18:53 this is driving me insane. 2013-12-28 18:53 who the hell is resetting PSW. 2013-12-28 18:58 JewFro297, have you seen zet86? 2013-12-28 18:59 pretty cool project :) 2013-12-28 19:00 seems to work well, according to the game screenshots 2013-12-28 19:01 Yup, I actually just made an opencores account so I can look at source for reference if I need to 2013-12-28 19:03 JewFro297, and yes, use migen, just don't replicate something that already exists 2013-12-28 19:04 would be cool to show a softcore written in migen 2013-12-28 19:08 Of course, copying isn't my thing. 2013-12-28 19:12 sb0_: funny, the zet project seems to reuse some Milkymist cores (fml and csr) 2013-12-28 19:21 yeah, there aren't that many options when you want an open source SDRAM controller that actually works 2013-12-28 19:21 mrueg has quit [Remote host closed the connection] 2013-12-28 19:22 well, there's grlib too, but it's very complex 2013-12-28 19:22 mrueg has joined #m-labs 2013-12-28 19:22 mrueg has quit [Changing host] 2013-12-28 19:22 mrueg has joined #m-labs 2013-12-28 19:26 vga_backbuffer[5393] = splash_src[5393]; <= this disables PSW.DTLBE and PSW.EDTLBE 2013-12-28 19:26 I tried booting several times, it's always at index 5393 in the loop 2013-12-28 19:27 are you sure it's not an interrupt, like uart? 2013-12-28 19:27 there are a few uart lines before that, which do not disable PSW.dtlb 2013-12-28 19:27 and it happens during a loop with not uart output 2013-12-28 19:28 ok, but did the UART ISR run before that? 2013-12-28 19:28 in the middle of the loop 2013-12-28 19:28 yes, it ran a few times before that 2013-12-28 19:28 TX is using isr, right? 2013-12-28 19:30 I sent a lot of keystrokes very early during the BIOS bootup and it's still erasing PSW at index 5393 of the splashscreen loading loop 2013-12-28 19:31 here is my instrumentation : http://pastebin.com/baeGd6q6 2013-12-28 19:32 well, sometimes it's i=5392 ... 2013-12-28 19:32 so it's not always the exact same index :o 2013-12-28 19:32 I don't think the timer is used in the BIOS 2013-12-28 19:34 mumptai has joined #m-labs 2013-12-28 19:35 sb0_: there is a TMU ISR right before the bug! 2013-12-28 19:37 ah. got it 2013-12-28 19:37 the tmu_isr does some load/stores 2013-12-28 19:37 hummm but tlb should be of 2013-12-28 19:37 off* 2013-12-28 19:37 * ysionneau does not get it 2013-12-28 19:48 sb0_: it's definetely due to TMU, I just commented the "CSR_TMU_CTL = td->flags|TMU_CTL_START;" line and PSW always keeps the good expected value :) 2013-12-28 19:48 I still don't get why the TMU isr would fuck up the PSW 2013-12-28 19:49 even if, by chance, the TMU isr fires when LM32 is servicing a dtlb miss, interrupts should be off and the TMU isr should only be serviced after return from exception 2013-12-28 19:52 maybe there is a race condition between Interrupts and TLB exceptions 2013-12-28 19:52 hard to simulate/debug :( 2013-12-28 19:54 if such a race condition exists, then it's understandable that it happens during this big load-store loop 2013-12-28 19:55 since we have an ISR firing regularly (TMU isr) and a big copy loop 2013-12-28 19:55 after some loop iteration there is a high chance that the ISR will end up firing at the right moment for the race condition to happen 2013-12-28 20:35 balrog has quit [Read error: Operation timed out] 2013-12-28 20:46 balrog has joined #m-labs 2013-12-28 21:14 Alarm has joined #m-labs 2013-12-28 22:49 Alarm has quit [Quit: ChatZilla 0.9.90.1 [Firefox 26.0/20131205075310]] 2013-12-28 23:42 sb0_ has quit [Quit: Leaving] 2013-12-28 23:44 JewFro297 has quit [Ping timeout: 272 seconds] 2013-12-29 01:10 kmehall has joined #m-labs 2013-12-29 01:15 kmehall has quit [] 2013-12-29 01:15 kmehall has joined #m-labs 2013-12-29 01:53 mumptai has quit [Quit: Verlassend] 2013-12-29 03:34 xiangfu has quit [Ping timeout: 260 seconds] 2013-12-29 03:37 mami_ has quit [Quit: leaving] 2013-12-29 03:38 mami has joined #m-labs 2013-12-29 04:08 JewFro297 has joined #m-labs 2013-12-29 04:22 Hawk777 has quit [Ping timeout: 240 seconds] 2013-12-29 05:18 JewFro297 has quit [Ping timeout: 272 seconds] 2013-12-29 05:35 Hawk777 has joined #m-labs 2013-12-29 06:17 xiangfu has joined #m-labs 2013-12-29 09:34 sb0 has joined #m-labs 2013-12-29 10:01 sb0 has quit [Ping timeout: 260 seconds] 2013-12-29 10:03 Alarm has joined #m-labs 2013-12-29 10:07 sb0 has joined #m-labs 2013-12-29 14:14 mumptai has joined #m-labs 2013-12-29 15:10 kristian1aul has quit [Remote host closed the connection] 2013-12-29 15:15 kristianpaul has joined #m-labs 2013-12-29 15:15 kristianpaul has joined #m-labs 2013-12-29 15:28 Scopeuk has joined #m-labs 2013-12-29 15:28 barmstro1g has joined #m-labs 2013-12-29 15:28 juliusb has joined #m-labs 2013-12-29 15:29 kristianpaul has quit [Ping timeout: 272 seconds] 2013-12-29 15:33 kristianpaul has joined #m-labs 2013-12-29 15:33 kristianpaul has quit [Changing host] 2013-12-29 15:33 kristianpaul has joined #m-labs 2013-12-29 15:33 Scopeuk_ has quit [*.net *.split] 2013-12-29 15:33 barmstrong has quit [*.net *.split] 2013-12-29 16:02 wpwrak_ has joined #m-labs 2013-12-29 16:02 wpwrak has quit [Read error: Connection reset by peer] 2013-12-29 16:34 JewFro297 has joined #m-labs 2013-12-29 16:45 Alarm has quit [Ping timeout: 245 seconds] 2013-12-29 18:04 kristianpaul has quit [Ping timeout: 246 seconds] 2013-12-29 18:06 kristianpaul has joined #m-labs 2013-12-29 18:08 felix_ has quit [Ping timeout: 264 seconds] 2013-12-29 18:08 felix_ has joined #m-labs 2013-12-29 18:28 kristianpaul has quit [Ping timeout: 260 seconds] 2013-12-29 18:28 kristianpaul has joined #m-labs 2013-12-29 18:38 sb0_ has joined #m-labs 2013-12-29 18:41 sb0 has quit [Ping timeout: 252 seconds] 2013-12-29 20:05 Alarm has joined #m-labs 2013-12-29 20:13 http://www.youtube.com/watch?v=5t7qO-RbqTw 2013-12-29 20:23 hmm, LED-blinky and slower-than-slowtan6 Actel FPGA? 2013-12-29 20:24 sb0_, hey they want to do arduino for 2013-12-29 20:24 and java. urgh. 2013-12-29 20:24 on the first day, god created the blinking LED ... :) 2013-12-29 20:24 FPGAs 2013-12-29 20:26 I wonder if Actel will still survive long. seriously, their FPGAs are so slow you can often replace them with a fast ARM MCU 2013-12-29 20:26 and benefit from incomparably better software tools. Actel didn't just fuck up their silicon, their software is also much worse than ISE. 2013-12-29 20:26 ah, he has made a PSHDL -> VHDL translator. no synthesis then. 2013-12-29 20:27 i like the way germans often use english swear words excessively :) 2013-12-29 20:27 actel is more or less a niche market provider, imho 2013-12-29 20:32 mhmm, a browser-based IDE? 2013-12-29 20:34 that's all the rage now, e.g., this one too: http://mbed.org/ 2013-12-29 20:35 urks 2013-12-29 20:44 why do they all go crazy on their 2013-12-29 20:44 pcb shapes? 2013-12-29 20:45 somehow you have to differentiate yourself from the competetion 2013-12-29 20:46 like placing 100mil headers in a non-100-mil grid? 2013-12-29 20:47 like, rounded down to 0.08 attoparsec ? 2013-12-29 20:50 more like: nooobody will use a perfboard, or a solderless breadboard, EVER .. 2013-12-29 20:53 well, it's been many many years that i touched one of these ... 2013-12-29 20:57 sorry, i was stretching the arduino analogy, the arduino people seem to be using them all the time 2013-12-29 20:58 it's getting less and less useful with less and less dip chips 2013-12-29 20:59 but for blinking a LED it should be enough 2013-12-29 21:00 dip parts are more or less replaced with small carrier pcbs, but its kinda limited to certain applications .. 2013-12-29 22:10 Alarm has quit [Ping timeout: 245 seconds] 2013-12-29 22:42 kyak has quit [Ping timeout: 252 seconds] 2013-12-29 23:10 Alarm has joined #m-labs 2013-12-29 23:51 sb0_ has quit [Quit: Leaving] 2013-12-30 00:03 asper has quit [Ping timeout: 260 seconds] 2013-12-30 00:04 asper has joined #m-labs 2013-12-30 01:20 mumptai has quit [Remote host closed the connection] 2013-12-30 03:19 xiangfu has quit [Ping timeout: 272 seconds] 2013-12-30 06:47 JewFro297 has quit [Ping timeout: 272 seconds] 2013-12-30 07:22 Alarm has quit [Quit: ChatZilla 0.9.90.1 [Firefox 26.0/20131205075310]] 2013-12-30 07:30 xiangfu has joined #m-labs 2013-12-30 07:42 xiangfu has quit [Quit: leaving] 2013-12-30 07:42 xiangfu has joined #m-labs 2013-12-30 08:44 Alarm has joined #m-labs 2013-12-30 09:11 sb0 has joined #m-labs 2013-12-30 09:12 kyak has joined #m-labs 2013-12-30 09:50 Alarm has quit [Ping timeout: 260 seconds] 2013-12-30 12:03 mrueg_ has joined #m-labs 2013-12-30 12:05 gric_ has joined #m-labs 2013-12-30 12:05 os1r1s_ has joined #m-labs 2013-12-30 12:06 balrog has quit [Ping timeout: 272 seconds] 2013-12-30 12:06 gric has quit [Ping timeout: 272 seconds] 2013-12-30 12:06 mrueg has quit [Ping timeout: 272 seconds] 2013-12-30 12:06 os1r1s has quit [Ping timeout: 272 seconds] 2013-12-30 12:06 balrog_ has joined #m-labs 2013-12-30 12:06 os1r1s_ is now known as os1r1s 2013-12-30 12:08 balrog_ is now known as balrog 2013-12-30 12:31 mrueg_ has quit [Changing host] 2013-12-30 12:31 mrueg_ has joined #m-labs 2013-12-30 14:20 sb0 has quit [Read error: Connection reset by peer] 2013-12-30 14:55 sb0 has joined #m-labs 2013-12-30 15:17 JewFro297 has joined #m-labs 2013-12-30 16:10 mumptai has joined #m-labs 2013-12-30 17:45 Alarm has joined #m-labs 2013-12-30 18:08 Alarm has quit [Remote host closed the connection] 2013-12-30 18:15 godkiefka has joined #m-labs 2013-12-30 18:15 paraboloid has joined #m-labs 2013-12-30 18:19 godkiefka has quit [Read error: Connection reset by peer] 2013-12-30 18:19 paraboloid has quit [Remote host closed the connection] 2013-12-30 18:26 windlove has joined #m-labs 2013-12-30 18:27 windlove has quit [Remote host closed the connection] 2013-12-30 18:33 So, does Wishbone interconnect allow for data transfer from different clock domains? 2013-12-30 18:42 sb0 has quit [Ping timeout: 246 seconds] 2013-12-30 18:55 sb0 has joined #m-labs 2013-12-30 19:42 JewFro297, wishbone itself no; but you can have two wishbone buses, one in each clock domain, and have some bridge core between the two 2013-12-30 20:09 larsc has quit [Remote host closed the connection] 2013-12-30 20:09 larsc has joined #m-labs 2013-12-30 20:15 is there actually a bus with built-in clock-domain crossing? 2013-12-30 20:22 depends on what you mean by built-in 2013-12-30 20:22 AXI works fine if you add a fifo on the bus for domain crossing 2013-12-30 20:22 or whatever else 2013-12-30 20:23 you want to use for domain crossing 2013-12-30 20:25 it's basically message based and the messages only ever travel in one direction 2013-12-30 20:26 so when you want to cross clock domains you can use your faviourite clock-domain crossing method 2013-12-30 20:26 so in a sense there is no built-in support for it, since it doesn't require anything special 2013-12-30 20:26 mhmm, arbittration gotta be more tricky with it ;) 2013-12-30 20:30 it's super easy ;) 2013-12-30 20:40 wasnÄ 2013-12-30 20:41 wasn't it capable of out-of-order transfers? 2013-12-30 20:42 * mumptai has to read overview & introduction again 2013-12-30 20:53 axi3 was, but this was dropped for axi4 2013-12-30 20:53 azonenberg has quit [Read error: Connection reset by peer] 2013-12-30 20:55 azonenberg has joined #m-labs 2013-12-30 20:55 so, the default implementation is buffered cross-bar, with optional cd-crossing in the buffers? 2013-12-30 20:56 I don't think there is a default implementation 2013-12-30 20:57 but yea, that sounds about right for a typical implementation 2013-12-30 20:57 you don't need the buffers though if you don't care about throughput 2013-12-30 20:58 you can always choose the buffer implementation, per port ;) 2013-12-30 21:11 xiangfu has quit [Ping timeout: 260 seconds] 2013-12-30 21:14 xiangfu has joined #m-labs 2013-12-30 21:25 ahmm, axi is amba, tought was something from opencores :| 2013-12-30 21:28 well it's royalty free and the specification is available 2013-12-30 22:10 but no bfm and references? 2013-12-30 22:50 sb0 has quit [Quit: Leaving] 2013-12-30 23:35 mumptai has quit [Quit: Verlassend] 2013-12-31 01:58 kristianpaul has quit [Remote host closed the connection] 2013-12-31 02:19 rterziev has joined #m-labs 2013-12-31 02:21 oleginchat has joined #m-labs 2013-12-31 02:29 rterziev has quit [Remote host closed the connection] 2013-12-31 02:29 oleginchat has quit [Remote host closed the connection] 2013-12-31 06:38 JewFro297 has quit [Ping timeout: 252 seconds] 2013-12-31 08:35 mumptai has joined #m-labs 2013-12-31 11:33 the pshdl guy got at least one thing right, he has a board for 30 euros 2013-12-31 11:48 his title page said it should be like arduino, what else is there to say? 2013-12-31 11:49 arduinos sold pretty well 2013-12-31 11:52 but technology wise they are limited and the design was never up to date, ignores many best-practises, contains trivial errors and is now locked into is own (backward) compatibility trap 2013-12-31 11:52 but educationally and commercially a huge success 2013-12-31 11:53 and arguably "better" hat basicstampes and pic-axe products ... if its only for the avr and gcc 2013-12-31 11:55 s/hat/than/ 2013-12-31 11:55 (sorry for my typing, still recovering from an arm injury) 2013-12-31 12:06 sb0 has joined #m-labs 2013-12-31 12:07 larsc, as long as the maker community doesn't move away from 30-euro hacks, there is no room for serious stuff 2013-12-31 12:11 and they have money. but they spend it on Apple products :-) 2013-12-31 12:11 sb0 has quit [Quit: Leaving] 2013-12-31 12:14 it is similar with hobbyist robotics 2013-12-31 12:17 but we got a lot of good and rather cheap parts availiable now, but people are only adapting them slowly and are rather reluctant to spend more than 50€ or more than a weekend on anything new 2013-12-31 12:20 those that wanted to do this 10 years ago had to spend a few 1k€ or crawl ebay for months and years, now it can be done with a few 100€ and COTS parts, but the numbers of people haven't really climbed that much 2013-12-31 12:24 the good thing about cheap stuff in my opinion is that it might introduce the subject to people who wouldn't have considered it otherwise 2013-12-31 12:24 and some of those persons than might go on an do serious stuff 2013-12-31 12:29 yeah, arduino might have done more for future generations of engineers than a lot of industrial engineers and academics 2013-12-31 12:47 antgreen has quit [Ping timeout: 252 seconds] 2013-12-31 13:00 wpwrak_ has quit [Ping timeout: 246 seconds] 2013-12-31 13:14 antgreen has joined #m-labs 2013-12-31 14:29 azonenberg has quit [*.net *.split] 2013-12-31 14:35 azonenberg has joined #m-labs 2013-12-31 15:46 JewFro297 has joined #m-labs 2013-12-31 15:49 kandobell has joined #m-labs 2013-12-31 15:49 emirov has joined #m-labs 2013-12-31 16:01 emirov has quit [K-Lined] 2013-12-31 16:01 kandobell has quit [K-Lined] 2013-12-31 16:03 guten rutsch 2013-12-31 16:04 mumptai has quit [Quit: Verlassend] 2013-12-31 18:41 mrueg_ has quit [Read error: Operation timed out] 2013-12-31 18:43 mrueg has joined #m-labs 2013-12-31 20:18 stekern has quit [Ping timeout: 245 seconds] 2013-12-31 20:18 stekern has joined #m-labs 2013-12-31 20:38 barmstro1g is now known as barmstrong 2013-12-31 20:38 hmm, I'm thinking of making a patch so that Memory's init accepts a dict or a list. if you use dicts, you can do a sparse initialization 2013-12-31 20:38 any objections? 2013-12-31 20:39 nevermind, i'll just unroll it into a list before calling :) 2013-12-31 20:48 how do i peek around the Memory's values at simulation time? 2013-12-31 21:03 actually, nevermind, it doesn't even seem to be sim-compatible since it has no get_fragment? i'm not sure how that part works 2013-12-31 22:46 i think i'm running into some timing weirdness. i swapped out a memory module i made for the migen one and am getting some really strange issues with signals seemingly not updating 2013-12-31 22:46 it's probably my own bug, but i'm curious if this is a known issue? 2013-12-31 23:24 Hawk777 has quit [Ping timeout: 252 seconds] 2013-12-31 23:24 Hawk777 has joined #m-labs 2013-12-31 23:47 happy new year :)