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2013-12-11 12:34 <whitequark> http://irclog.whitequark.org/m-labs
2013-12-11 12:34 <lekernel> thx
2013-12-11 12:34 lekernel changed the topic of #m-labs to: Mixxeo, Migen, MiSoC & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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2013-12-11 20:47 <lekernel> 3'sd1 - 3'sd4 = 5
2013-12-11 20:47 <lekernel> https://www.destroyallsoftware.com/talks/wat
2013-12-11 20:56 <lekernel> ...what actually happens is that 4 is the sign bit in "3'sd4", which gets extended to -4 when the target is more than 3 bits. and it becomes 1 - (-4) = 5
2013-12-11 20:58 <lekernel> thus the rule: in verilog, when you want to represent the most negative integer, you should write its absolute (positive) value instead :)
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2013-12-11 21:33 <GitHub36> [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/d2s6Dg
2013-12-11 21:33 <GitHub36> migen/master 135a4fe Sebastien Bourdeauducq: fhdl/verilog: fix representation of negative integers...
2013-12-11 21:36 <lekernel> rjo, your test passes now. -1'sd1 was 1 in Verilog :)
2013-12-11 21:40 <rjo> lekernel: that's horrible ;)
2013-12-11 21:40 <rjo> lekernel: thanks for looking into this. i didn't have the guts to dive that deep into verilog.
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2013-12-11 21:43 <rjo> lekernel: that means verilog does sign extend literal constants even when they do not have a "-" that would indicate their negativity?
2013-12-11 21:43 <lekernel> it sign-extends operands when the context is signed
2013-12-11 21:44 <lekernel> the signedness of the context is defined by the signedness of all operands
2013-12-11 21:44 <lekernel> and you can mark literal constants as signed by using 's
2013-12-11 21:45 <lekernel> in which case the MSB is the sign bit, and you have to set it manually - using the unary minus before the literal fails for the most negative integer, as we have seen :)
2013-12-11 21:46 <lekernel> you can also mark any part of an expression as signed by using $signed (Migen inserts those to provide better sign extension rules)
2013-12-11 21:51 <rjo> lekernel: would writing -4'sd4 not work in a 3-bit signed context?
2013-12-11 21:53 <lekernel> it would work
2013-12-11 21:56 <rjo> lekernel: would it not be more readable?
2013-12-11 21:56 <lekernel> but because that literal would make it a 4-bit context
2013-12-11 21:56 <lekernel> it would make it more readable, but then, it breaks the rule that literals use their minimum number of bits
2013-12-11 21:57 <lekernel> which can cause problems e.g. when putting them in Cat() or Replicate()
2013-12-11 21:58 <lekernel> btw, check out this horrible presentation http://www.sutherland-hdl.com/papers/2006-SNUG-Boston_standard_gotchas_presentation.pdf
2013-12-11 22:01 <mumptai> hey, it contains pixelated men and pretty colors ;)
2013-12-11 22:04 <rjo> lekernel: ok. understood. but i dont see why verilog is unable to represent the most negative integer using a unary minus. i do understand why 3'sd4 is "wrong" in the sense that it either invalid or -4. But why is -3'sd4 not -4? Just because --3'sd4 != 3'sd4 then?
2013-12-11 22:04 <lekernel> because 3'sd4 is -4
2013-12-11 22:04 <rjo> that presentation seriously lacks some WordArt and yellow text.
2013-12-11 22:05 <lekernel> as the 3rd bit (MSB) is the sign bit, which would have weight 4 if the value wasn't signed
2013-12-11 22:05 <rjo> lekernel: wouldn't you want 3'sd4 to be invalid in a better world?
2013-12-11 22:06 <lekernel> yes, but then you can't represent -4, as the unary minus won't let you
2013-12-11 22:08 <lekernel> (you need an extra bit to represent the absolute value of the most negative integer)
2013-12-11 22:09 <rjo> lekernel: hmm
2013-12-11 22:10 <lekernel> right now, migen spits out the explicit two's complement representation of the value, and tells Verilog to treat the MSB as sign bit
2013-12-11 22:11 <lekernel> it's a straightforward solution, which has the inconvenience of making negative values less readable in the generated code
2013-12-11 22:12 <lekernel> and you get things like 1'sd1 for -1, which is horrible, but works ...
2013-12-11 22:16 <rjo> lekernel: so this is the only way to represent the most negative signed integer without wrongly increasing the bit-width of the context?
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2013-12-11 22:18 <lekernel> I think so
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2013-12-11 22:23 <lekernel> ah, no
2013-12-11 22:23 <lekernel> -1'd1 works
2013-12-11 22:23 <lekernel> :)
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2013-12-11 22:26 <lekernel> hmm, actually, I could have simply dropped the "s", since the unary minus also makes the context signed
2013-12-11 22:30 <lekernel> ah, no, it does not
2013-12-11 22:30 <lekernel> -1'd1*5'sd5 is 155
2013-12-11 22:30 <lekernel> 1'sd1*5'sd5 is -5 as one would expect
2013-12-11 22:31 <lekernel> $signed(-1'd1)*5'sd5 also works
2013-12-11 22:31 <lekernel> but is quite heavy
2013-12-11 22:31 <lekernel> Verilog is such a terrible language o__O
2013-12-11 22:34 <lekernel> rjo, so, which is less bad?
2013-12-11 22:35 <lekernel> 1) $signed(-'d<human readable value>)
2013-12-11 22:35 <lekernel> 2) 'sd<explicit two's complement value>
2013-12-11 22:35 <lekernel> 3) 'sd<explicit two's complement value> /* <human readable value> */
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